1. Instructor: Yuzhuang Hu yhu1@cs.sfu.ca

2. Final August 7, 2009 7:00pm - 10:pm HCC1700

4. I/O Interface Units Peripherals are often eletro-mechanical devices whose manner of operation is different from that of the CPU and memory. The data-transfer rate of peripherals is usually different from the clock rate of the CPU. Data codes and formats in peripherals differ from the word format in the CPU. The operating modes of peripherals differ from each other.

5. I/O bus and interface

11. Modes of Transfer Data transfer under program control. Interrupt-initiated data transfer. Direct memory access transfer.

12. Program-Controlled Transfer

13. Interrupt-Initiated Transfer SP <- SP – 1Decrement stack pointer M[SP] <- PCStore return address on stack SP <- SP – 1 Decrement stack pointer M[SP] <- PSRStore processor status word on stack EI <- 0Reset enable-interrupt flip-flop INTACK <- 1Enable interrupt acknowledge PC <- IVADTransfer interrupt vector address to PC, go to fetch phase

16. Final August 7, 2009 7:00pm - 10:pm HCC1700

17. Sequential Circuit Design

21. Design from ASM processor statuscontrol pts SEQ CTRL PTS SELECTOR External control inputs Data inData out Clock

22. VHDL Write some VHDL codes. Processes in VHDL.

23. Pipeline Execution of the instructions in each stage. Hazards. Find data and control hazards. Avoid data and control hazards. Insert NOP Change the order of the instructions Other methods

25. Data hazards Consider the following instructions 1.MOV R1, R5 2.ADD R2, R1, R6 3.ADD R3, R1, R2 IFDOFEXWB IFDOFEXWB IFDOFEXWB 123 4 5 Mov R1, R5 Add R2, R1, R6 Add R3, R1, R2

26. Cache Memory 32 bit address, 1024 KB cache, 4 word line, two way associative cache Question: how many bits in tag and index? tag index block byte

29. Overall picture

30. THANKS!