1. High Speed Digital System Lab Spring 2009 1 semester project  Instructor: Mony Orbach  Students: Pavel Shpilberg Ohad Fundoianu Ohad Fundoianu

2.  Definition  Theoretical Background  Project targets  Block diagram  Schematic diagram  Programmable parameters  Time table

3.  Examining Stratix card ability of GX (protocols and parameters).  Testing the channel by checking the distortion of signals along the lines using high speed scope.  Implementation of High Speed Serial channel on Stratix 2 GX board.

4. Serial Out  Transceiver – used for transmitting/receiving data in the PHY.  PHY – The physical layer of the OSI model consists of PCS, PMA and PMD - physical medium. PMA Analog Section PCS Digital Section n n FPGA m m  Applications – Gigabit Ethernet systems, wireless network routers, fiber optic and communication systems. Serial In

5. Amplitude dependent Noise:  CrossTalk: Capacitive & Inductive Coupling Shared Signal Return  ISI: Reflections, Oscillations, Inertial Delay.  Timing: Skew, Jitter.  Power Suppluy Noise.

6. Independent Noise:  Skin Effect  Ohmic Loss  Dielectric Loss

7. Serilizer Encoding PLL DeserilizerDecoding

8. ReceiverTransmitter PLL Memory HS Scope Output clock

9.  8/10 B  Transmit Buffer  Pre-Emphasis  Receiver Input Buffer  Equalizer  PLL/CRU Clock

10. 23/1230/126/1214/121/130/15/2 Learning how to use high speed scope, and labs board. Implementing the HS channel at highest speed, with out 10/8 bit. Examining Programmable Parameters Generating Distortions Using Lab's Board and Analyzing them on scope Final Presentation and Project Book