1. 1 204521 Digital Computer Architecture Lecture 10b I/O Introduction: Storage Devices, Metrics, & Productivity Pradondet Nilagupta Original note from Professor David A. Patterson Spring 2001

2. 2 204521 Digital Computer Architecture Storage System Issues Historical Context of Storage I/O Secondary and Tertiary Storage Devices Storage I/O Performance Measures Processor Interface Issues A Little Queuing Theory Redundant Arrarys of Inexpensive Disks (RAID) I/O Buses

3. 3 204521 Digital Computer Architecture A Communication-Centric World Computation is getting distributed … –Internet, WAN, LAN, BodyLAN, Home Networks, Microprocessor Peripherals, Processor-Memory Interface, System-on-a-Chip Efficient Networking and Communication is Crucial The System-on-a-Chip implies the Network- on-a-Chip In Next Set of Lectures: –Busses and Networks –But more importantly, the impact of integration

4. 4 204521 Digital Computer Architecture A Bus Is: shared communication link single set of wires used to connect multiple subsystems A Bus is also a fundamental tool for composing large, complex systems –systematic means of abstraction Control Datapath Memory Processor Input Output What is a bus?

5. 5 204521 Digital Computer Architecture Busses

6. 6 204521 Digital Computer Architecture Versatility: –New devices can be added easily –Peripherals can be moved between computer systems that use the same bus standard Low Cost: –A single set of wires is shared in multiple ways Memory Processe r I/O Device Advantages of Buses

7. 7 204521 Digital Computer Architecture It creates a communication bottleneck –The bandwidth of that bus can limit the maximum I/O throughput The maximum bus speed is largely limited by: –The length of the bus –The number of devices on the bus –The need to support a range of devices with: Widely varying latencies Widely varying data transfer rates Memor y Processo r I/O Device Disadvantage of Buses

8. 8 204521 Digital Computer Architecture Control lines: –Signal requests and acknowledgments –Indicate what type of information is on the data lines Data lines carry information between the source and the destination: –Data and Addresses –Complex commands Data Lines Control Lines General Organization of a Bus

9. 9 204521 Digital Computer Architecture A bus transaction includes two parts: –Issuing the command (and address) – request –Transferring the data – action Master is the one who starts the bus transaction by: –issuing the command (and address) Slave is the one who responds to the address by: –Sending data to the master if the master ask for data –Receiving data from the master if the master wants to send data Bus Master Bus Slave Master issues command Data can go either way Master versus Slave

10. 10 204521 Digital Computer Architecture Types of Busses Processor-Memory Bus (design specific) –Short and high speed –Only need to match the memory system Maximize memory-to-processor bandwidth –Connects directly to the processor –Optimized for cache block transfers I/O Bus (industry standard) –Usually is lengthy and slower –Need to match a wide range of I/O devices –Connects to the processor-memory bus or backplane bus Backplane Bus (standard or proprietary) –Backplane: an interconnection structure within the chassis –Allow processors, memory, and I/O devices to coexist –Cost advantage: one bus for all components

11. 11 204521 Digital Computer Architecture Processor/Memory Bus PCI Bus I/O Busses Example: Pentium System Organization

12. 12 204521 Digital Computer Architecture A Computer System with One Bus: Backplane Bus A single bus (the backplane bus) is used for: –Processor to memory communication –Communication between I/O devices and memory Advantages: Simple and low cost Disadvantages: slow and the bus can become a major bottleneck Example: IBM PC - AT ProcessorMemory I/O Devices Backplane Bus

13. 13 204521 Digital Computer Architecture A Two-Bus System I/O buses tap into the processor-memory bus via bus adaptors: –Processor-memory bus: mainly for processor-memory traffic –I/O buses: provide expansion slots for I/O devices Apple Macintosh-II –NuBus: Processor, memory, and a few selected I/O devices –SCCI Bus: the rest of the I/O devices ProcessorMemory I/O Bus Processor Memory Bus Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus I/O Bus

14. 14 204521 Digital Computer Architecture A Three-Bus System A small number of backplane buses tap into the processor-memory bus –Processor-memory bus is only used for processor-memory traffic –I/O buses are connected to the backplane bus Advantage: loading on the processor bus is greatly reduced ProcessorMemory Processor Memory Bus Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus Backplane Bus I/O Bus

15. 15 204521 Digital Computer Architecture North/South Bridge architectures: separate busses Separate sets of pins for different functions –Memory bus –Caches –Graphics bus (for fast frame buffer) –I/O busses are connected to the backplane bus Advantage: –Busses can run at different speeds –Much less overall loading! ProcessorMemory Processor Memory Bus Bus Adaptor Bus Adaptor I/O Bus Backplane Bus I/O Bus “backside cache”

16. 16 204521 Digital Computer Architecture Bunch of Wires Physical / Mechanical Characteristics – the connectors Electrical Specification Timing and Signaling Specification Transaction Protocol What defines a bus?

17. 17 204521 Digital Computer Architecture Synchronous Bus: –Includes a clock in the control lines –A fixed protocol for communication that is relative to the clock –Advantage: involves very little logic and can run very fast –Disadvantages: Every device on the bus must run at the same clock rate To avoid clock skew, they cannot be long if they are fast Asynchronous Bus: –It is not clocked –It can accommodate a wide range of devices –It can be lengthened without worrying about clock skew –It requires a handshaking protocol Synchronous and Asynchronous Bus

18. 18 204521 Digital Computer Architecture ° ° ° MasterSlave Control Lines Address Lines Data Lines Bus Master: has ability to control the bus, initiates transaction Bus Slave: module activated by the transaction Bus Communication Protocol: specification of sequence of events and timing requirements in transferring information. Asynchronous Bus Transfers: control lines (req, ack) serve to orchestrate sequencing. Synchronous Bus Transfers: sequence relative to common clock. Busses so far

19. 19 204521 Digital Computer Architecture Bus Transaction Arbitration: Who gets the bus Request: What do we want to do Action: What happens in response

20. 20 204521 Digital Computer Architecture One of the most important issues in bus design: –How is the bus reserved by a device that wishes to use it? Chaos is avoided by a master-slave arrangement: –Only the bus master can control access to the bus: It initiates and controls all bus requests –A slave responds to read and write requests The simplest system: –Processor is the only bus master –All bus requests must be controlled by the processor –Major drawback: the processor is involved in every transaction Bus Master Bus Slave Control: Master initiates requests Data can go either way Arbitration: Obtaining Access to the Bus

21. 21 204521 Digital Computer Architecture Multiple Potential Bus Masters: the Need for Arbitration Bus arbitration scheme: –A bus master wanting to use the bus asserts the bus request –A bus master cannot use the bus until its request is granted –A bus master must signal to the arbiter the end of the bus utilization Bus arbitration schemes usually try to balance two factors: –Bus priority: the highest priority device should be serviced first –Fairness: Even the lowest priority device should never be completely locked out from the bus Bus arbitration schemes can be divided into four broad classes: –Daisy chain arbitration –Centralized, parallel arbitration –Distributed arbitration by self-selection: each device wanting the bus places a code indicating its identity on the bus. –Distributed arbitration by collision detection: Each device just “ goes for it ”. Problems found after the fact.

22. 22 204521 Digital Computer Architecture The Daisy Chain Bus Arbitrations Scheme Advantage: simple Disadvantages: –Cannot assure fairness: A low-priority device may be locked out indefinitely –The use of the daisy chain grant signal also limits the bus speed Bus Arbiter Device 1 Highes t Priorit y Device N Lowest Priority Device 2 Grant Release Request wired-OR

23. 23 204521 Digital Computer Architecture Used in essentially all processor-memory busses and in high-speed I/O busses Bus Arbiter Device 1 Device N Device 2 Grant Req Centralized Parallel Arbitration

24. 24 204521 Digital Computer Architecture All agents operate synchronously All can source / sink data at same rate => simple protocol –just manage the source and target Simplest bus paradigm

25. 25 204521 Digital Computer Architecture Even memory busses are more complex than this –memory (slave) may take time to respond –it may need to control data rate BReq BG Cmd+Addr R/W Address Data1Data2 Data Simple Synchronous Protocol

26. 26 204521 Digital Computer Architecture Slave indicates when it is prepared for data xfer Actual transfer goes at bus rate BReq BG Cmd+Addr R/W Address Data1Data2 Data Data1 Wait Typical Synchronous Protocol

27. 27 204521 Digital Computer Architecture Separate versus multiplexed address and data lines: –Address and data can be transmitted in one bus cycle if separate address and data lines are available –Cost: (a) more bus lines, (b) increased complexity Data bus width: –By increasing the width of the data bus, transfers of multiple words require fewer bus cycles –Example: SPARCstation 20 ’ s memory bus is 128 bit wide –Cost: more bus lines Block transfers: –Allow the bus to transfer multiple words in back-to-back bus cycles –Only one address needs to be sent at the beginning –The bus is not released until the last word is transferred –Cost: (a) increased complexity (b) decreased response time for request Increasing the Bus Bandwidth

28. 28 204521 Digital Computer Architecture Overlapped arbitration –perform arbitration for next transaction during current transaction Bus parking –master holds onto bus and performs multiple transactions as long as no other master makes request Overlapped address / data phases –requires one of the above techniques Split-phase (or packet switched) bus –completely separate address and data phases –arbitrate separately for each –address phase yield a tag which is matched with data phase ” All of the above ” in most modern memory buses Increasing Transaction Rate on Multimaster Bus

29. 29 204521 Digital Computer Architecture BusMBusSummitChallengeXDBus OriginatorSunHPSGISun Clock Rate (MHz)40604866 Address lines364840muxed Data lines64128256144 (parity) Data Sizes (bits)2565121024512 Clocks/transfer454? Peak (MB/s)320(80)96012001056 MasterMultiMultiMultiMulti ArbitrationCentralCentralCentralCentral Slots16910 Busses/system1112 Length13 inches12? inches17 inches 1993 CPU- Memory Bus Survey

30. 30 204521 Digital Computer Architecture Address Data Read Req Ack Master Asserts Address Master Asserts Data Next Address Write Transaction t0 t1 t2 t3 t4 t5 t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target t1: Master asserts request line t2: Slave asserts ack, indicating data received t3: Master releases req t4: Slave releases ack Asynchronous Handshake (4- phase)

31. 31 204521 Digital Computer Architecture Address Data Read Req Ack Master Asserts AddressNext Address t0 t1 t2 t3 t4 t5 t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target\ t1: Master asserts request line t2: Slave asserts ack, indicating ready to transmit data t3: Master releases req, data received t4: Slave releases ack Read Transaction Slave Data

32. 32 204521 Digital Computer Architecture BusSBusTurboChannelMicroChannelPCI OriginatorSunDECIBMIntel Clock Rate (MHz)16-2512.5-25async33 AddressingVirtualPhysicalPhysicalPhysical Data Sizes (bits)8,16,328,16,24,328,16,24,32,648,16,24,32,64 MasterMultiSingleMultiMulti ArbitrationCentralCentralCentralCentral 32 bit read (MB/s)33252033 Peak (MB/s)898475111 (222) Max Power (W)16261325 1993 Backplane/IO Bus Survey

33. 33 204521 Digital Computer Architecture Examples –graphics –fast networks Limited number of devices Data transfer bursts at full rate DMA transfers important –small controller spools stream of bytes to or from memory Either side may need to squelch transfer –buffers fill up High Speed I/O Bus

34. 34 204521 Digital Computer Architecture All signals sampled on rising edge Centralized Parallel Arbitration –overlapped with previous transaction All transfers are (unlimited) bursts Address phase starts by asserting FRAME# Next cycle “ initiator ” asserts cmd and address Data transfers happen on when –IRDY# asserted by master when ready to transfer data –TRDY# asserted by target when ready to transfer data –transfer when both asserted on rising edge FRAME# deasserted when master intends to complete only one more data transfer PCI Read/Write Transactions

35. 35 204521 Digital Computer Architecture – Turn-around cycle on any signal driven by more than one agent PCI Read Transaction

36. 36 204521 Digital Computer Architecture PCI Write Transaction

37. 37 204521 Digital Computer Architecture The System-on-a-Chip Nightmare Bridge DMACPUDSP Mem Ctrl. MPEG C IOO System Bus Peripheral Bus Control Wires Custom Interfaces The “ Board-on-a-Chip ” Approach

38. 38 204521 Digital Computer Architecture Sonics SOC Integration Architecture SiliconBackplane Agent ™ Open Core Protocol ™ SiliconBackplane ™ (patented) MultiChip Backplane ™ { DSP MPEG CPU DMA C MEM IO

39. 39 204521 Digital Computer Architecture Open Core Protocol Goals Bus Independent Scalable Configurable Synthesis/Timing Analysis Friendly Encompass entire core/system interface needs (data, control, and test flows)

40. 40 204521 Digital Computer Architecture Data, Control, and Test Flows Data Flow –Signals and protocols associated with moving data –Includes address, data, handshaking, etc. –Similar to services provided by traditional computer buses Control Flow –Signals and protocols associated with non-data communication –Sideband - not synchronized to data flow (out of band) –Examples include interrupts, high-level flow control, etc. Test Flow –Signals and protocols related to debug and manufacturing test

41. 41 204521 Digital Computer Architecture OCP Overview Point-to-point, uni-directional, synchronous –easy physical implementation Master/Slave, request/response –well-defined, simple roles Extensions –added functionality to support cores with more complex interface requirements Configurability –pay only for the features needed for a given core

42. 42 204521 Digital Computer Architecture Master vs. Slave IP Core On-Chip Bus Slave MasterSlave Master InitiatorTarget Open Core Protocol Request Response

43. 43 204521 Digital Computer Architecture Basic OCP Master MCmd [3] MAddr [N] MData [N] SResp [3] SData [N] Clk SCmdAccept Read: Command, Address Command Accept Response, Data Write (posted): Command, Address, Data Command Accept MCmd, MAddr SCmdAccept SResp, SData MCmd, Maddr, MData SCmdAccept Slave

44. 44 204521 Digital Computer Architecture Protocol Phases Request Phase (begins Transfer) –Master presents request (command, address, etc.) to Slave Response Phase (ends Transfer) –Slave presents response (success/fail, read data) to Master –Only available for read transfers (posted write model) Datahandshake Phase (Optional) –Allows pipelining request ahead of write data –Only available for write transfers Phase ordering –Request -> Datahandshake -> Response

45. 45 204521 Digital Computer Architecture OCP Extensions Simple Extensions –Byte Enables –Bursts –Flow Control –Data Handshake Complex Extensions –Threads and Connections Sideband Signals

46. 46 204521 Digital Computer Architecture The Backplane: Why Not Use a Computer Bus? IP Core IP Core IP Core IP Core Computer Bus Transmit FIFOReceive FIFO Time Data ArbiterAddress Expensive to decouple Not designed for real-time

47. 47 204521 Digital Computer Architecture Communication Buses Decouple and Guarantee Real Time IP Core IP Core IP Core IP Core Communications Bus Transmit FIFOReceive FIFO Time Data TDMA Connections are expensive Poor read latency

48. 48 204521 Digital Computer Architecture From Communications Efficient BW decoupling Guaranteed BW & latency Side-band signaling SiliconBackplane ™ Employs Best of Both From Computing Address-based selection Write and read transfers Pipelining DSP MPEG CPU DMA C MEM IO

49. 49 204521 Digital Computer Architecture Guaranteed Bandwidth Arbitration Independent arbitration for every cycle includes two phases: -Distributed TDMA -Round robin Provides fine control over system bandwidth Current Slot Arbitration Command

50. 50 204521 Digital Computer Architecture Guaranteed Latency Fixed latency between command/address and data/response phases Matches pipelined CPU model ensuring high performance access to on-chip resources Pipelined data routed through SiliconBackplane ™ Latency re-programmable in software Variable-latency blocks do not tie up the SiliconBackplane

51. 51 204521 Digital Computer Architecture Pipeline Diagram

52. 52 204521 Digital Computer Architecture Integrated Signaling Mechanism Dedicated SiliconBackplane ™ wires ( Flags ) support: –Bus-style out-of-band signaling (interrupts) –Point-to-point communications (flow control) –Dynamic point-to-point (retry mechanism) Same design flow, timing, flexibility as address/data portion of SonicsIA ™

53. 53 204521 Digital Computer Architecture MultiChip Backplane SiliconBackplane MultiChip Backplane ™ Extends SonicsIA ™ Between Chips CPU-Based ASSP ASSP FPGA Seamless integration of protocols

54. 54 204521 Digital Computer Architecture Validation / Test SiliconBackplane ™ highly visible for test –All subsystems communicate through SiliconBackplane Test Interfaces: –MultiChip Backplane: 100 ’ s MB/sec. –ServiceAgent: Scan-based Each subsystem can be tested/validated stand-alone Test Vectors Test Vectors MultiChip Backplane ™

55. 55 204521 Digital Computer Architecture Summary Busses are an important technique for building large-scale systems –Their speed is critically dependent on factors such as length, number of devices, etc. –Critically limited by capacitance –Tricks: esoteric drive technology such as GTL Important terminology: –Master: The device that can initiate new transactions –Slaves: Devices that respond to the master Two types of bus timing: –Synchronous: bus includes clock –Asynchronous: no clock, just REQ/ACK strobing System-on-a-Chip approach invites new solutions –Well-defined and clear communication protocols –Physical layer hidden to designer

56. 56 204521 Digital Computer Architecture Interconnect Trends Interconnect = glue that interfaces computer system components High speed hardware interfaces + logical protocols Networks, channels, backplanes memory-mapped wide pathways centralized arb message-based narrow pathways distributed arb

57. 57 204521 Digital Computer Architecture Backplane Architectures Distinctions begin to blur: SCSI channel is like a bus FutureBus is like a channel (disconnect/reconnect) HIPPI forms links in high speed switching fabrics

58. 58 204521 Digital Computer Architecture Bus-Based Interconnect Bus: a shared communication link between subsystems –Low cost: a single set of wires is shared multiple ways –Versatility: Easy to add new devices & peripherals may even be ported between computers using common bus Disadvantage –A communication bottleneck, possibly limiting the maximum I/O throughput Bus speed is limited by physical factors –the bus length –the number of devices (and, hence, bus loading). –these physical limits prevent arbitrary bus speedup.

59. 59 204521 Digital Computer Architecture Bus-Based Interconnect Two generic types of busses: –I/O busses: lengthy, many types of devices connected, wide range in the data bandwidth), and follow a bus standard (sometimes called a channel) –CPU – memory buses: high speed, matched to the memory system to maximize memory – CPU bandwidth, single device (sometimes called a backplane) –To lower costs, low cost (older) systems combine together Bus transaction –Sending address & receiving or sending data

60. 60 204521 Digital Computer Architecture Bus Protocols ฐ ฐ ฐฐ ฐ ฐ MasterSlave Control Lines Address Lines Data Lines Multibus: 20 address, 16 data, 5 control, 50ns Pause Bus Master : has ability to control the bus, initiates transaction Bus Slave : module activated by the transaction Bus Communication Protocol : specification of sequence of events and timing requirements in transferring information. Asynchronous Bus Transfers: control lines (req., ack.) serve to orchestrate sequencing Synchronous Bus Transfers: sequence relative to common clock

61. 61 204521 Digital Computer Architecture Synchronous Bus Protocols Address Data Read Wait Clock Address Data Wait Pipelined/Split transaction Bus Protocol addr 1 data 0 addr 2 wait 1 data 1 addr 3 OK 1 data 2 begin read Read complete

62. 62 204521 Digital Computer Architecture Asynchronous Handshake Address Data Read Req. Ack. Master Asserts Address Master Asserts Data Next Address Write Transaction t0 t1 t2 t3 t4 t5 t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target\ t1: Master asserts request line t2: Slave asserts ack, indicating data received t3: Master releases req t4: Slave releases ack 4 Cycle Handshake

63. 63 204521 Digital Computer Architecture Read Transaction Address Data Read Req Ack Master Asserts AddressNext Address t0 t1 t2 t3 t4 t5 Time Multiplexed Bus: address and data share lines t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target\ t1: Master asserts request line t2: Slave asserts ack, indicating ready to transmit data t3: Master releases req, data received t4: Slave releases ack 4 Cycle Handshake

64. 64 204521 Digital Computer Architecture Bus Arbitration Parallel (Centralized) Arbitration Serial Arbitration (daisy chaining) Polling BR BG M M M M BGi BGo BR M BGi BGo BR M BGi BGo BR BG BR A.U. BR A C M M M BR A A.U. Bus Request Bus Grant

65. 65 204521 Digital Computer Architecture Bus Options OptionHigh performanceLow cost Bus widthSeparate addressMultiplex address & data lines& data lines Data widthWider is fasterNarrower is cheaper (e.g., 32 bits)(e.g., 8 bits) Transfer sizeMultiple words hasSingle-word transfer less bus overheadis simpler Bus mastersMultipleSingle master (requires arbitration)(no arbitration) Split Yes — separate No — continuous transaction?Request and Replyconnection is cheaper packets gets higher and has lower latency bandwidth (needs multiple masters) ClockingSynchronousAsynchronous

66. 66 204521 Digital Computer Architecture 1990 Bus Survey (P&H, 1st Ed) VME FutureBus Multibus IIIPISCSI Signals1289696168 Addr/Data muxnoyesyesn/an/a Data width16 - 323232168 Mastersmultimultimultisinglemulti ClockingAsyncAsyncSyncAsynceither MB/s (0ns, word) 253720251.5 (asyn) 5 (sync) 150ns word12.915.510== 0ns block27.995.240== 150ns block13.620.813.3== Max devices21202187 Max meters0.50.50.55025 Standard IEEE 1014 IEEE 896.1 ANSI/IEEE ANSI X3.129 ANSI X3.131 1296

67. 67 204521 Digital Computer Architecture VME 3 96-pin connectors 128 defined as standard, rest customer defined –32 address –32 data –64 command & power/ground lines

68. 68 204521 Digital Computer Architecture SCSI: Small Computer System Interface Clock rate: 5 MHz / 10 MHz (fast) / 20 MHz (ultra) Width: n = 8 bits / 16 bits (wide); up to n – 1 devices to communicate on a bus or “ string ” Devices can be slave ( “ target ” ) or master( “ initiator ” ) SCSI protocol: a series of “ phases ”, during which specif- ic actions are taken by the controller and the SCSI disks –Bus Free: No device is currently accessing the bus –Arbitration: When the SCSI bus goes free, multiple devices may request (arbitrate for) the bus; fixed priority by address –Selection: informs the target that it will participate (Reselection if disconnected) –Command: the initiator reads the SCSI command bytes from host memory and sends them to the target –Data Transfer: data in or out, initiator: target –Message Phase: message in or out, initiator: target (identify, save/restore data pointer, disconnect, command complete) –Status Phase: target, just before command complete

69. 69 204521 Digital Computer Architecture SCSI “ Bus ” : Channel Architecture peer-to-peer protocols initiator/target linear byte streams disconnect/reconnect

70. 70 204521 Digital Computer Architecture 1993 I/O Bus Survey (P&H, 2nd Ed) BusSBusTurboChannelMicroChannelPCI OriginatorSunDECIBMIntel Clock Rate (MHz)16-2512.5-25async33 AddressingVirtualPhysicalPhysicalPhysical Data Sizes (bits)8,16,328,16,24,328,16,24,32,648,16,24,32,64 MasterMultiSingleMultiMulti ArbitrationCentralCentralCentralCentral 32 bit read (MB/s)33252033 Peak (MB/s)898475111 (222) Max Power (W)16261325

71. 71 204521 Digital Computer Architecture 1993 MP Server Memory Bus Survey BusSummitChallengeXDBus OriginatorHPSGISun Clock Rate (MHz)604866 Split transaction?YesYes Yes? Address lines4840?? Data lines128256144 (parity) Data Sizes (bits)5121024512 Clocks/transfer454? Peak (MB/s)96012001056 MasterMultiMultiMulti ArbitrationCentralCentralCentral AddressingPhysicalPhysicalPhysical Slots16910 Busses/system112 Length13 inches12? inches17 inches

72. 72 204521 Digital Computer Architecture Communications Networks Performance limiter is memory system, OS overhead Send/receive queues in processor memories Network controller copies back and forth via DMA No host intervention needed Interrupt host when message sent or received

73. 73 204521 Digital Computer Architecture I/O Controller Architecture Request/response block interface Backdoor access to host memory

74. 74 204521 Digital Computer Architecture I/O Data Flow Impediment to high performance: multiple copies, complex hierarchy