1. Bus Mr. Mukul Varshney

2. Bus A bus, in computing, is a set of physical connections (cables, printed circuits, etc.) which can be shared by multiple hardware components in order to communicate with one another. The purpose of buses is to reduce the number of "pathways" needed for communication between the components, by carrying out all communications over a single data channel. This is why the metaphor of a "data highway" is sometimes used. Mr. Mukul Varshney

3. Bus

4. Characteristics of a bus Characteristics of a bus A bus is characterised by the amount of information that can be transmitted at once. This amount, expressed in bits, corresponds to the number of physical lines over which data is sent simultaneously. A 32-wire ribbon cable can transmit 32 bits in parallel. The term "width" is used to refer to the number of bits that a bus can transmit at once. Additionally, the bus speed is also defined by its frequency (expressed in Hertz), the number of data packets sent or received per second. Each time that data is sent or received is called a cycle. Mr. Mukul Varshney

5. Characteristics of Bus This way, it is possible to find the maximum transfer speed of the bus, the amount of data which it can transport per unit of time, by multiplying its width by its frequency. A bus with a width of 16 bits and a frequency of 133 MHz, therefore, has a transfer speed equal to: 16 * 133.10 6 = 2128*10 6 bit/s, or 2128*10 6 /8 = 266*10 6 bytes/s or 266*10 6 /1000 = 266*10 3 KB/s or 266*10 3 /1000 = 266 MB/s Mr. Mukul Varshney

6. 6 Advantages of Buses Versatility: ◦ New devices can be added easily ◦ Peripheral devices can be moved between computer systems that use the same bus standard Low Cost: ◦ A single set of wires is shared in multiple ways Provides a way to manage the complexity of design ◦ Device only has to implement the bus standard. Memory Processor I/O Device

7. 7 Disadvantage of Buses It creates a communication bottleneck ◦ Bus bandwidth can limit the maximum I/O throughput The maximum bus speed is largely limited by: ◦ The length of the bus ◦ The number of devices on the bus ◦ The need to support a range of devices with:  Widely varying latencies  Widely varying data transfer rates Memory Processor I/O Device

8. Kinds of bus inside the System There are three main bus groups  ADDRESS BUS  DATA BUS  CONTROL BUS Mr. Mukul Varshney

9. Data Bus The Data Bus carries the data which is transferred throughout the system. It is bi-directional. Examples of data transfers – Program instructions being read from memory into MPU. – Data being sent from CPU to I/O port – Data being read from I/O port going to CPU – Results from CPU sent to Memory These are called read and write operations Data Bus Mr. Mukul Varshney

10. Address Bus An address is a binary number that identifies a specific memory storage location or I/O port involved in a data transfer The Address Bus is used to transmit the address of the location to the memory or the I/O port. The Address Bus is unidirectional (one way): addresses are always issued by the CPU. Address Bus Mr. Mukul Varshney

11. Control Bus The Control Bus: is another group of signals whose functions are to provide synchronization (timing control) between the MPU and the other system components. Control signals are unidirectional, and are mainly outputs from the MPU. Example Control signals – RD: read signal asserted to read data into MPU – WR: write signal asserted to write data from MPU Control Bus Mr. Mukul Varshney

12. Single Bus system Mr. Mukul Varshney

13. multiple bus system Mr. Mukul Varshney

14. Types of bus- 1.Processor-memory Buses – Short, high speed – Designed to maximize memory-processor bandwidth – Only need to match the memory system Maximize memory-to-processor bandwidth – Connects directly to the processor – Optimized for cache block transfers 2.I/O Buses – Usually is lengthy and slower – Wide range in bandwidth – Does not interface directly with memory, Uses processor-memory bus or backplane bus – Need to match a wide range of I/O devices Mr. Mukul Varshney

15. 3.Backplane Buses – Allow processors, memory and I/O devices to coexist on single bus – Balance demands of processor-memory communication with demands of I/O device-memory communication – Interconnects the circuit boards containing processor, memory and I/O – The backplane is an interconnection structure within the chassis – Used as an intermediary bus connecting I/O busses to the processor-memory bus – Cost advantage: one bus for all components Mr. Mukul Varshney

16. Synchronous vs Asynchronous Bus Synchronous buses ◦ Clock in the control lines and a fixed protocol for communication ◦ Relatively fast because protocol is predetermined Disadvantages ◦ All bus devices run on same clock rate ◦ Clock skew problem constraint on length of bus Asynchronous Buses ◦ Have no clock signal ◦ Wide variety of devices running at different speeds ◦ Uses handshaking protocol-  Additional control lines needed: ReadReq, DataRdy, and Ack Mr. Mukul Varshney

17. 17 Asynchronous vs. Synchronous bus Advantages of asynchronous bus: ◦ Eliminates the need for synchronization between the sender and the receiver. ◦ Can accommodate varying delays automatically, using the Slave-ready signal. Disadvantages of asynchronous bus: ◦ Data transfer rate with full handshake is limited by two-round trip delays. ◦ Data transfers using a synchronous bus involves only one round trip delay, and hence a synchronous bus can achieve faster rates.

18. CSE 141 - Buses 18 System with only one bus A single bus (the backplane bus) is used for: ◦ Processor to memory communication ◦ Communication between I/O devices and memory Advantages: Simple and low cost Disadvantage: slow - the bus is a major bottleneck Example: IBM PC – AT (ancient history) ProcessorMemory I/O Devices Backplane Bus

19. CSE 141 - Buses 19 A Two-Bus System I/O buses tap into the processor-memory bus via bus adaptors: ◦ Processor-memory bus: mainly for processor-memory traffic ◦ I/O buses: provide expansion slots for I/O devices ProcessorMemory I/O Bus Processor Memory Bus Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus I/O Bus

20. CSE 141 - Buses 20 A Three-Bus System Backplane bus taps into the processor-memory bus ◦ I/O buses are connected to the backplane bus Advantage: much less load on the processor bus. ProcessorMemory Processor Memory Bus Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus Backplane Bus I/O Bus

21. Bus Arbitration Bus arbitration means settlement among different modules. Bus arbiter decides which module work firstly. Bus arbitration is a way of sharing the computer's data transferring channels (buses) in an optimal way so the faster devices won't have to wait to be able to transfer and the slower devices (like peripherals) will have a chance to transfer as well. Different methods exist but two main types are the serial and parallel arbitrations. Serials include the daisy chain arbitration and hardware polling. The parallel ones are software polling and independent requesting. Mr. Mukul Varshney

22. The Need for Bus Arbitration Multiple devices may need to use the bus at the same time so must have a way to arbitrate multiple requests Bus arbitration schemes usually try to balance: ◦ Bus priority – the highest priority device should be serviced first ◦ Fairness – even the lowest priority device should never be completely locked out from the bus Bus arbitration schemes can be divided into four classes ◦ Daisy chain arbitration – see next slide ◦ Centralized, parallel arbitration – see next-next slide ◦ Distributed arbitration by self-selection – each device wanting the bus places a code indicating its identity on the bus ◦ Distributed arbitration by collision detection – device uses the bus when its not busy and if a collision happens (because some other device also decides to use the bus) then the device tries again later (Ethernet)

23. Serial Arbitration Scheme : Daisy Chain Bus Arbitration Advantage: simple Disadvantages: ◦ Cannot assure fairness – a low-priority device may be locked out indefinitely ◦ Slower – the daisy chain grant signal limits the bus speed Bus Arbiter Device 1 Highest Priority Device N Lowest Priority Device 2 Ack Release Request wired-OR Data/Addr

24. Serial Arbitration Scheme cont. The processor connected to the system bus are assigned priority according to their position along the priority control line. When multiple devices concurrently request the use of the bus, the device with the highest priority is granted access to it. It is assumed that each processor had its own bus arbiter logic with priority in and priority out lines. Mr. Mukul Varshney

25. Serial Bus arbitration cont. The [priority-out] PO of each arbiter is connected to the [priority-in] PI of the next lower priority arbiter. The PI of the highest priority unit is maintained at logic 1 value. If the processor requests control of the bus, and the corresponding arbiter finds its PI input equal to 1 it sets its PO output to 0. Thus the processor whose arbiter has a PI=1 and PO=0 is the one that has the control of the bus. Mr. Mukul Varshney

26. Centralized Parallel Arbitration Advantages: flexible, can assure fairness Disadvantages: more complicated arbiter hardware Used in essentially all processor-memory buses and in high-speed I/O buses Bus Arbiter Device 1 Device NDevice 2 Grant1 Data/Addr Grant2 GrantN Request1Request2RequestN

27. Parallel Arbitration logic Bus Arbiter 1 Ack Req Bus Arbiter2 Ack Req Bus Arbiter3 Ack Req Bus Arbiter 4 Ack Req 4 X 2 Priority Encoder 2 X 4 Decoder Bus busy line Mr. Mukul Varshney

28. Parallel arbitration cont. It uses an external priority encoder and a decoder. Each bus arbiter has a request output line and a bus acknowledge input line. For requesting a bus arbiter enables its request line. The arbiter takes control of the bus if its acknowledge input line is enabled. Bus busy line provides an orderly transfer of control. Mr. Mukul Varshney

29. Priority Encoder 4 X 2 Priority Encoder 1101 2 x 4 Decoder 00 INPUTOutpu t I0I0 I1I1 I2I2 I3I3 XY 1XXX00 01XX01 001X10 000111 0000XX I 0 I 1 I 2 I 3 X Y 1 0 0 0 Mr. Mukul Varshney

30. Parallel Bus Abitration: Dynamic Arbitration Algorithm (1) Time Slice: This algorithm allocates a fixed length time slice of bus time that is offered sequentially to each processor in round robin fashion. No preference is given to any particular device since each is allotted the Same amount of time to communicate with the bus. Mr. Mukul Varshney

31. Dynamic Arbitration Algorithm (2) Polling: Here the bus grant signal is replaced by a set of lines called poll lines which are connected to all units. These lines are used by the bus controller to define an address for each device. The bus controller sequences through the addresses in a prescribed manner. When a processor that require access recognizes its address, it activates the bus busy lines and then access the bus Mr. Mukul Varshney

32. Dynamic Arbitration Algorithm (3) Least Recently Used: This algorithm gives the highest priority to the requesting device that has not used the bus for the longest interval. (4) FCFS: Requests are served in the order they are received. Mr. Mukul Varshney

33. Dynamic Arbitration Algorithm (5) Rotating daisy Chain: In this scheme there is no central bus controller, and the priority line is connected from the PO of last device back to the PI of first device in a close loop. The device which access the bus serves as bus controller. Each arbiter priority for a given bus cycle is determined by its position along the bus priority line from the arbiter whose processor is currently controlling the bus. Mr. Mukul Varshney