1. ASIC, Customer-Owned Tooling, and Processor Design Nancy Nettleton Manager, VLSI ASIC Device Engineering April 2000 Design Style Myths That Lead EDA Astray

2. Design Style Myths  COT is a design style that achieves higher performance through greater ownership of physical design.  ASICs are slower than processors because of design margin.  Design automation tactics tuned on processors are effective on ASICs if they are more heavily automated.

3. Evolution of the ASIC Design Flow Synthesis Floorplan Placement Timing Closure Routing Late 90’s 018um-0.25um Synthesis Floorplan Placement Timing Closure Routing Xcap Closure Today <=0.15um SynthesisPlacement Routing Early 90’s 0.6um-1.0um Synthesis Floorplan Placement Routing Mid-90’s 0.35um-0.5um COT? Customer ASIC Supplier

4. Difference Between ASIC & COT Wafer Yield Final Test Yield Fab Package/ Assembly/ Test Tested Parts Physical Design Logical Design Netlist + Timing Constraints GDSII ASIC SupplierCustomer FoundryPkg/Test  ASIC model: ASIC supplier responsible for physical design, silicon fabrication, & package/assembly/test.  COT model: Customer responsible for physical design, wafer, and final test yield.

5. Meaning of Customer-Owned Tooling Has Changed  Used to mean who owned physical design, the foundry or the customer.  Now it means who is responsible for the supply chain, regardless of the design flow used.  The term Customer-Owned Tooling  No longer defines a design flow.  Transfer of silicon responsibility from a vertically integrated ASIC supplier to the customer (with commensurate cost reduction).

6. Implications of Yield Ownership Was the wafer processed correctly? Was the design properly targeted within process distribution? Two Types of Yield ASIC Supplier ASIC Supplier ASIC Model Foundry Customer COT Model Physical design determines target within a process distribution. Clock Power Signal Integrity Performance Verification

7. Yield and Performance ASICs target full yield at target performance. Clock rate often defined by system interface No value in running faster. Non-functional if slower. Processors typically do not target full yield at target performance. Marketable at many performance points. Added value for higher performance parts, even if yield is limited. Can still sell slower parts.

8. Microprocessor Design Flow Overview RTL Custom Circuit Design Custom Layout Memory Design Custom Layout Datapath Mapping Datapath Compilation Synthesis Place & Route Chip Integration Reduced Emphasis on Synth’d Logic UltraSparcI/II20+% UltrasparcIII15% Next Gen Sparc5% Most Like ASIC

9. Key Differences in Design Content ASICProcessor Synthesized Logic Memory Datapath Custom Circuit Design Dominated by synthesized logic Dominated by custom circuit design. Compiled memories embedded in logic. Custom memories as independent blocks. Heavily partitioned.Lightly partitioned.

10. Key Methodology Differences ASICProcessor Delay Calculation Circuit Simulation Timing Sign-off SynthesizedCustom Power & Clock100’s of K gates10’s of K gatesBlock SizeModeledSimulatedNoise AnalysisAutomatedManualTiming ClosureAutomatedManualNoise Repair

11. Migrating to COT ASIC SupplierCustomer Fab Package/ Assembly/ Test Physical Logical ASIC Customer Foundry Pkg/Test Fab Package/ Assembly/ Test Physical Logical COT More Custom Tuning? Not Necessarily...

12. If Customer Owns Physical Design, Why Not Tune It?  ASIC content is fundamentally different than processor content.  Volatile system IP is partitioned onto ASICs  Highly tuned system interfaces  Definition evolves right up to system power-on.  Rapid silicon implementation is often more important than detailed tuning.  Even if customer owns physical design, the nature of the system IP may prohibit design tuning.  Then why go COT? $ $ $ $ $ $ $ $ $ $

13. Different Design Objectives  Processor  System chips  More stable architecture (through partitioning)  Achieve best possible timing  Less stable architecture (because of system partitioning)  Achieve acceptable timing on limited number of well-understood critical paths. on large number of unknown critical paths.

14. Implications  Processors becoming increasingly unsuitable as proving grounds for prevalent silicon design techniques.  Excellent vehicles for circuit design and performance-related problems.  Not representative of system chips  Small, homogeneous synthesized logic blocks  Heavily partitioned and tuned  Less automation.

15. Conclusion  Customer-Owned Tooling is a business model, not a design style.  Ownership of physical design does not equate to higher performance.  Performance of system chips is often defined by IP and schedule, not design techniques.  Heavy partitioning and custom circuit design make processor design increasingly less representative of system chip automation.