1. December, 2004 Ecole Polytechnique 1 Deterministic BIST By Amiri Amir Mohammad Professor Dr. Abdelhakim Khouas Project Presentation for ELE6306 (Test des Circuits Electronics)

2. December, 2004 2Ecole Polytechnique Deterministic BIST Schemes To Discuss Schemes To Discuss I. DBIST Schemes Based On Reseeding of LFSR I. DBIST Schemes Based On Reseeding of LFSR A. General DBIST Scheme A. General DBIST Scheme B. Implicit Encoding ( Re-ordering Of Patterns) B. Implicit Encoding ( Re-ordering Of Patterns) C. Implicit Encoding( Reordering 2Of Test cubes+ next-bit ) C. Implicit Encoding( Reordering 2Of Test cubes+ next-bit ) II. DBIST Schemes Using Internal Patterns II. DBIST Schemes Using Internal Patterns A. Bit-Flipping BIST (BFF) A. Bit-Flipping BIST (BFF) B. Improved BFF BIST (SMF) B. Improved BFF BIST (SMF) III. Others III. Others SMF with Multiple Scan SMF with Multiple Scan DBIST with TPI DBIST with TPI

3. December, 2004 3Ecole Polytechnique BIST OVERVIEW PRPG PRPG Random patterns by LFSR with P(x) Random patterns by LFSR with P(x) Signature Analysis by MISR Signature Analysis by MISR Large number of Patterns to achieve FC Large number of Patterns to achieve FC Delay & performance issues Delay & performance issues Deterministic Deterministic Complex Algorithms Complex Algorithms Increased Complexity for larger and complex circuits Increased Complexity for larger and complex circuits Many patterns needed to achieve desired FC Many patterns needed to achieve desired FC Delay and Costly Delay and Costly

4. December, 2004 4Ecole Polytechnique Deterministic BIST What? Improved BIST scheme Why? Increase FC in Scan-Based Design Improve test application time and performance How? Random Patterns + Deterministic Initially random patterns Generated by Internal LFSR Random resistant faults not detected Followed by Deterministic Patterns Generated by ATPG Tend to detect hard-to-detect faults (random resistant)

5. December, 2004 5Ecole Polytechnique I. DBIST (LFSR Reseeding) A. General Scheme A. General Scheme k-bit MP-LFSR Programmable k-bit MP-LFSR Programmable 2 k distinct patterns 2 k distinct patterns x primitive polynomials => x different sequences of patterns depending on initial value (seed) x primitive polynomials => x different sequences of patterns depending on initial value (seed) ATPG-generated deterministic pattern encoded into n-bit word ATPG-generated deterministic pattern encoded into n-bit word q -bit => Poly. Id (2 q Polynomials ) q -bit => Poly. Id (2 q Polynomials ) ( n - q ) bit => LFSR seed ( n - q ) bit => LFSR seed m -bit Scan Register m -bit Scan Register

6. December, 2004 6Ecole Polytechnique Behavior Behavior LFSR loaded with seed value LFSR loaded with seed value Poly ID identifies FeedBack configuration Poly ID identifies FeedBack configuration LFSR output bits serially shifted into the Scan Register in m-clocks LFSR output bits serially shifted into the Scan Register in m-clocks Generated pattern consistent with encoded deterministic pattern Generated pattern consistent with encoded deterministic pattern Original Test Cube - - 0 0 - - - 1 - 0 Original Test Cube - - 0 0 - - - 1 - 0 Generated pattern 1 1 0 0 101 1 0 0 Generated pattern 1 1 0 0 101 1 0 0 I. DBIST (LFSR Reseeding)

7. December, 2004 7Ecole Polytechnique Encoding Of Test Cubes Size of seed depends on number of carebits in Test Cube C carebit => specified bit either 1 or 0, not ‘x’ A set of test cubes T = { C1, C2,…, Ci } S(C i ) = { indice of carebits in test cube Ci } s(Ci) = Number of carebits in test cube Ci s max (T) = maximum number of specified bits in set T Example: T={ C1, C2, C3 } C1 = x1xx0x11xx, C2 = xxx10xx1xx, C3 = 0x1xxxx0xx S(C 1 ) = {2, 3, 5, 8} s(C 1 )=4 s(C 2 )=3 s(C 3 ) = 3 s max (T) = 4 a i consistent with c i * c i = a i = (a(0). M i ) 1 = (a(0).M i-k+1 ) k Companion matrix M I. DBIST (LFSR Reseeding)

8. December, 2004 8Ecole Polytechnique Encoding Of Test Cubes (continued..) To encode C into a seed a Solving s(C) system of non-linear equations in terms of seed variables(a 0, …, a k-1 ) & polynomial coefficients (p 0,…,p k-1 ), obtained from * Two way to solve: 1. Fixing seed variables, and finding the corresponding P(x) System of non-linear equations (complex to solve) 2. Fixing P(x), and finding seed variables Simpler to solve Less computation time in general If no solution with P 1 (x), choose next polynomial average # of polynomials analyzed slightly greater than one I. DBIST (LFSR Reseeding)

9. December, 2004 9Ecole Polytechnique Example: Given P (x) = x4 + x3 + 1 p 0 =1 p 1 =0 p 2 =0 p 3 =1 C = “x 1xx 0xx 11x” => S(C) = {1,2,5,8} and s(C) = 4. For each index i in S(C), calculate a(0). M i ik(M i-k+1 ) k cici a(0) k 11 M 1 1 1a0 22 M 1 2 1a1 53 M 3 3 0a2 84 M 5 4 1a3 (M i-k+1 ) k Calculated for each i and k Subscript k indicates k th position in the set of seed variables a(0) I. DBIST (LFSR Reseeding)

10. December, 2004 10Ecole Polytechnique Only 4-bit encoding for 10 bit test cube (4 + q)-bit stored in Memory I. DBIST (LFSR Reseeding)

11. December, 2004 11Ecole Polytechnique General Scheme Efficient Encoding Probabilistic Analysis show Very high probability of successfull encoding with s + 4 bits ( 16 polynomial LFSR ) Area Overhead N Patterns => N x (s + q) bits of storage Control Logic For configuration Optimization possible in terms of storage area I. DBIST (LFSR Reseeding)

12. December, 2004 12Ecole Polytechnique Modified Reseeding Scheme Re-ordering of Test Cubes Reduced Storage Size No storage for poly id Periodic Operation Mod-p counter p is the period of the sequence of polynomials (p feedback polynomials) Addition of Random Patterns to complete periods High Computational Effort B. Implicit Encoding Scheme (1) B. Implicit Encoding Scheme (1) I. DBIST (LFSR Reseeding)

13. December, 2004 13Ecole Polytechnique B. Implicit Encoding Scheme (1) ( Continued.. ) Periodic Operation Example: T = {C 1, C 2, C 3, C 4 } & set of Polynomials P(C) where P (C i ) contains all the polynomials that can generate C i P (C 1 ) = {p 1, p 4 }, P (C 2 ) = P (C 3 ) = {p 1, p 2, p 3, p 4 } P (C 4 ) = {p 2, p 3 } p1 and p2 can generate all the patterns (C1, C2) by p 1 ; (C3, C4) by p 2 Therefore: ( C 1, C 2, C 3, C 4 ) Implies Sequence of Polynomials (p1, p1, p2, p2) Re-ordering : (p1, p2, p1, p2) => ( C 1, C 3, C 2, C 4 ) minimum period 2 adding random patterns to make perfect ordering not necessary (i.e counter can be stopped in last period at any time) Can insert more polynomial from P(C i ) at the expense of AREA I. DBIST (LFSR Reseeding)

14. December, 2004 14Ecole Polytechnique B. Implicit Encoding Scheme (1) ( Continued.. ) Issue: achieve a re-ordering of the polynomials such that all the test cubes are covered, and so by having a sequence of polynomials with minimum period Therefore: Need An Algorithm to reduce the list of test cubes generated by each polynomial and hence reduce period TestCube Compaction To improve time of test application and the efficiency of encoding Techniques Simplification: Removal of Ci from T if Ci is a subsets of Cj Merging : consistent test cubes combined such that s(mrg(C 1 C 2 …Ci)) ≤ s(T) is met. Concatenation : Ci&Cj&…&Cz if s(concat(..)) ≤ s(T) I. DBIST (LFSR Reseeding)

15. December, 2004 15Ecole Polytechnique B. Implicit Encoding Scheme (1) ( Continued.. ) B. Implicit Encoding Scheme (1) ( Continued.. ) TestCube Compaction (Example): TestCube Compaction (Example): Simplification And Merging Simplification And Merging I. DBIST (LFSR Reseeding)

16. December, 2004 16Ecole Polytechnique B. Implicit Encoding Scheme (1) (Continued..) B. Implicit Encoding Scheme (1) (Continued..) TestCube Compaction (Example..): TestCube Compaction (Example..): Concatenation Concatenation Only 3 encoding needed as opposed to 4. Only 3 encoding needed as opposed to 4. Therefore, Reduced Encoding and consequently improved time of test application can be obtained Therefore, Reduced Encoding and consequently improved time of test application can be obtained I. DBIST (LFSR Reseeding)

17. December, 2004 17Ecole Polytechnique Modified Reseeding Scheme Modified Reseeding Scheme Re-ordering of Test Cubes Re-ordering of Test Cubes Reduced Storage Size Reduced Storage Size Seed grouping Seed grouping Storage required for Next-bit Storage required for Next-bit q-bit counter q-bit counter Each state of Counter correponds to a feedback configuration Each state of Counter correponds to a feedback configuration No Balancing needed in the number of seeds No Balancing needed in the number of seeds (s max + 1) x N storage for N patterns (s max + 1) x N storage for N patterns B. Implicit Encoding Scheme (2) B. Implicit Encoding Scheme (2) I. DBIST (LFSR Reseeding)

18. December, 2004 18Ecole Polytechnique A. Bit Flipping BIST (BFF) ( Continued.. ) A. Bit Flipping BIST (BFF) ( Continued.. ) Pattern mapping Pattern mapping Useless random patterns converted into deterministic Useless random patterns converted into deterministic BFF block is combinational and responsible to flip an output bit of LFSR at particular states of LFSR BFF block is combinational and responsible to flip an output bit of LFSR at particular states of LFSR II. DBIST Scheme Using Internal Patterns

19. December, 2004 19Ecole Polytechnique Efficient Mapping Efficient Mapping P r and P d with minimum humming distance P r and P d with minimum humming distance Minimum cost (least number of minterms) Minimum cost (least number of minterms) Random Pattern Pr Random Pattern Pr Pr = f ( LFSR states ) Pr = f ( LFSR states ) On-set(Pr): Modifiable bits On-set(Pr): Modifiable bits Off-set(Pr): fixed bits (consistent with Pd ) Off-set(Pr): fixed bits (consistent with Pd ) Fix-set: Fix-set: On-, Off-, Fix-sets contain LFSR states On-, Off-, Fix-sets contain LFSR states {s 0, s 1, …, s k-1 } {s 0, s 1, …, s k-1 } A. Bit Flipping BIST (BFF) ( Continued.. ) A. Bit Flipping BIST (BFF) ( Continued.. ) II. DBIST Scheme Using Internal Patterns

20. December, 2004 20Ecole Polytechnique BFF function Constructed iteratively starting with BFF 0 ending with BFF R in R iterations At each iteration r ( 0 ≤ r ≤ R ) New P d embeded in BFF More Hard-to-detect faults coverd New set of Hard-to-detect faults F identified Final BFF R covers all faults Fix 0 set of LFSR states, whose random patterns detect some faults A. Bit Flipping BIST (BFF) ( Continued.. ) A. Bit Flipping BIST (BFF) ( Continued.. ) II. DBIST Scheme Using Internal Patterns

21. December, 2004 21Ecole Polytechnique Example: 3-bit LFSR, 5-bit Scan Register, F = {f 1, f 2, f 3, f 4, f 5 }, primitive P (x) generating s 0 -s 6 as below. Example: 3-bit LFSR, 5-bit Scan Register, F = {f 1, f 2, f 3, f 4, f 5 }, primitive P (x) generating s 0 -s 6 as below. s0 010 s1 001 s2 100 s3 110 s4 111 s5011 s6101 s7 = s0 …010… #Pattern LFSR states 101001 s0, s1, s2, s3, s4 2 11010 s5, s6, s0, s1, s2 3 01110 s3, s4, s5, s6, s0 410011 s1, s2, s3, s4, s5 510100 s6, s0, s1, s2, s3  Assume P1 = 11xxx and P2 = 0xx1x Covering f1, f2, f3  Fix1={s5, s6}Fix2={s3, s6}and Fix0 = Union(Fix1, Fix2} = {s3, s5, s6 }  BFF 0  BFF 0 = Ø and Fix0 = {s3, s5, s6 }  A determinstic pattern Pd = 11 x 01 covering f 4, f 5  Hence, need to map P d onto a Pr in the list A. Bit Flipping BIST (BFF) ( Continued.. ) A. Bit Flipping BIST (BFF) ( Continued.. ) II. DBIST Scheme Using Internal Patterns

22. December, 2004 22Ecole Polytechnique   Example (cont..):   on-set and off-set for all Pr w.r.t (Pd = 11 x 01)   Candidates for mapping P d : P 1, P 2, P 4. Why not P3, P5 ? P 1 chosen, because minimum cost (humming distance + least # of minterms )   New BFF = Union {BFF 0, on-set (P d, P 1 )} = { s0 }   New FIX = FIX 1 = Union {FIX 0, on-set (P d, P 1 ), off-set (P d, P 1 )} = {s0, s1, s3, s4, s5, s6} A. Bit Flipping BIST (BFF) ( Continued.. ) A. Bit Flipping BIST (BFF) ( Continued.. ) II. DBIST Scheme Using Internal Patterns

23. December, 2004 23Ecole Polytechnique  Minimizing BFF by considering s0 (on-set elements) only  New LFSR patterns =>  P d =  P d = 11 x 01  P1 = 11xxx P2 = 0xx1x  Randomly modified A. Bit Flipping BIST (BFF) ( Continued.. ) A. Bit Flipping BIST (BFF) ( Continued.. ) II. DBIST Scheme Using Internal Patterns

24. December, 2004 24Ecole Polytechnique Extension of BFF Extension of BFF Improves Area Overhead Improves Area Overhead Autocorrelation between random patterns Autocorrelation between random patterns 1111- 0111-1011-1101-1110 1111- 0111-1011-1101-1110 SMF = f ( LFSR states, Bit- counter bits, Pattern-counter bits) SMF = f ( LFSR states, Bit- counter bits, Pattern-counter bits) Same procedure as BFF to get SMF function, except state variables are different Same procedure as BFF to get SMF function, except state variables are different B. Improved BFF (SMF) B. Improved BFF (SMF) II. DBIST Scheme Using Internal Patterns

25. December, 2004 25Ecole Polytechnique Example : Given 2-bit LFSR with P(x) with states as below, test length 6, 5-bit Scan Register, and need to generate Example : Given 2-bit LFSR with P(x) with states as below, test length 6, 5-bit Scan Register, and need to generate P d1 = “00010, P d2 = “00011 P d1 = “00010, P d2 = “00011 Looking at the table Looking at the table Minimum of 2 bits need to be modified for a chosen Pr Minimum of 2 bits need to be modified for a chosen Pr B. Improved BFF (SMF) (continued..) B. Improved BFF (SMF) (continued..) II. DBIST Scheme Using Internal Patterns

26. December, 2004 26Ecole Polytechnique Example (continued.. ) Example (continued.. ) P d1, P d2 are similar P d1, P d2 are similar P d1 maps onto P 1 (minimum cost) P d1 maps onto P 1 (minimum cost) On 1 ( P d1, P 1 ) = { 000 000 01, 010 000 01} Off 1 ( P d1, P 1 ) = { 001 000 10, 011 000 01, 100 000 10} logic minimization similar to BFF logic minimization similar to BFF SMF 1 = {xx0 xxx x1} SMF 1 = {xx0 xxx x1} covering all terms of but none of covering all terms of On 1 ( Pd1, P1 ) but none of Off 1 ( Pd1, P1 ) Fix 1 = Union { On 1 ( Pd1, P1 ), Off 1 ( Pd1, P1 ) } To map P d2, repeated (P 4 ) is the candidate To map P d2, repeated P 1 (P 4 ) is the candidate B. Improved BFF (SMF) (continued..) B. Improved BFF (SMF) (continued..) II. DBIST Scheme Using Internal Patterns

27. December, 2004 27Ecole Polytechnique : SMF1: With the new table, only 1-bit modification possible for mapping P d2 On 2 ( P d2, P 4 ) = {100 011 10} Off 2 (P d2, P 4 ) = {000 011 01, 001 01110, 010 011 11, 011 011 01} and FIX 2 = Union { Fix1, Off 2 (P d2, P 4 ), On 2 ( P d2, P 4 ) } SMF 2 = {xx0 xxx x1, xx0 xx1 xx} = b 0. (p 0 + t 0 ) B. Improved BFF (SMF) (continued..) B. Improved BFF (SMF) (continued..) II. DBIST Scheme Using Internal Patterns

28. December, 2004 28Ecole Polytechnique  P d1 and P d2 mapped efficiently with only two minterms Original Pattern SMF1SMF2 10110 can100010 110110101001110 0110101000 1011000010 can200011 1101101010 011010100011000  SMF 2 : B. Improved BFF (SMF) (continued..) B. Improved BFF (SMF) (continued..) II. DBIST Scheme Using Internal Patterns

29. December, 2004 29Ecole Polytechnique  High FC compared to PRPG for  Less Area than the 32-bit register used for PRPG for the same FC  Less Area than BOTH (BFF and General)  Efficiency of the SMF over PRPG B. Improved BFF (SMF) (continued..) B. Improved BFF (SMF) (continued..) II. DBIST Scheme Using Internal Patterns Circuit Random FC SMF FC Area (% of LFSR-32) s83866.92%95.92%41.6% s923490.63%91.51%66.4% s1320793.83%96.38%43.8% s1585094.58%97.25%43.8% s3841793.41%93.62%46.9% s3858498.71%98.93%43.8% s267088.26%89.19%76.0% s755296.29%97.05%78.2% Circuit S-path length(n) Reseedin g [mm2] BFF [mm2] Area [mm2] s420340.3440.0630.057 s641540.3440.0630.052 s713540.3440.0630.051 s838660.5330.1000.090 s953450.3080.0630.050 s1196320.3350.0670.057 s1238320.3320.0630.057 s53782140.4230.0810.078 s92342470.9440.5440.448 s32077000.7300.1930.158 s158506110.9180.3310.327 s3841716641.8961.7331.492 s3858414640.7700.5770.294 s26701570.7340.2790.220 s75522060.9870.5170.384

30. December, 2004 30Ecole Polytechnique Improvement over single-scan SMF Improvement over single-scan SMF Breaking one large scan register into several scan registers Breaking one large scan register into several scan registers Reduced time of test application (less FFs) Similar Synthesis process as single scan SMF, except at logic minimization step Patterns feed several scan paths P d can map onto any path SMF with Multiple Scan III. Others Schemes

31. December, 2004 31Ecole Polytechnique DBIST with TPI DBIST with TPI BFF combined with TPI (Test point insertion) BFF combined with TPI (Test point insertion) Improves Improves Random testability Random testability Controllability and Observability Controllability and Observability 100% FC achieved with less area 100% FC achieved with less area DBIST Schemes DBIST Schemes III. Others Schemes

32. December, 2004 32Ecole Polytechnique Reseeding of LFSR Reseeding of LFSR General DBIST Scheme General DBIST Scheme High FC High FC Efficient Encoding ( Less computational effort for encoding of seeds) Efficient Encoding ( Less computational effort for encoding of seeds) Storage Area Overhead (seed + poly id ) Storage Area Overhead (seed + poly id ) Implicit Encoding (1) Implicit Encoding (1) High FC High FC Less Storage Area ; mod-p counter needed Less Storage Area ; mod-p counter needed More Computational effort needed for encoding of seeds More Computational effort needed for encoding of seeds Re-ordering needed + added Random Patterns for balancing Re-ordering needed + added Random Patterns for balancing Implicit Encoding (2) Implicit Encoding (2) High FC High FC next-bit + p-bit counter (for p polynomials of LFSR) next-bit + p-bit counter (for p polynomials of LFSR) No balancing problem, hence no random patterns need to be added No balancing problem, hence no random patterns need to be added VI. Conclusion DBIST Schemes DBIST Schemes

33. December, 2004 33Ecole Polytechnique VI. Conclusion Internal Pattern Generation Internal Pattern Generation BFF BFF High FC High FC Pattern Mapping Pattern Mapping Less Area Overhead (No Storage required) Less Area Overhead (No Storage required) Synthesis process Synthesis process SMF (single scan design) SMF (single scan design) High FC High FC Pattern Mapping Pattern Mapping Furthre improve BFF for area overhead ( reduced-size LFSR ) Furthre improve BFF for area overhead ( reduced-size LFSR ) Synthesis Process Synthesis Process SMF with Multiple Scan Register SMF with Multiple Scan Register improved time of test Application improved time of test Application DBIST Schemes DBIST Schemes

34. December, 2004 34Ecole Polytechnique