1. Exploring and Exploiting the Multilevel Parallelism Inside SSDs for Improved Performance and Endurance May 23, 2013 Beom Ju Shin IEEE Transactions on Computers, June 2013 Yang Hu, Hong Jiang, Dan Feng, Lei Tian, Hao Luo, and Chao Ren Huazhong University of Science & Technology (HUST)

2. Background Four levels of parallelism inside an SSD –Channel-level parallelism –Chip-level parallelism –Die-level parallelism –Plane-level parallelism Three internal factors to exploit the parallelism –Advanced commands –Address allocation schemes –Priority order of exploiting the four levels of parallelism

3. Goal –To find optimal priority order of exploiting the four levels of parallelism to maximize the performance of an SSD Six candidates –S1: chip-level > die-level > plane-level > channel-level parallelism –S2: channel-level > chip-level > die-level > plane-level parallelism –S3: channel-level > plane-level > chip-level > die-level parallelism –S4: channel-level > die-level > chip-level > plane-level parallelism –S5: channel-level > plane-level > die-level > chip-level parallelism –S6: channel-level > die-level > plane-level > chip-level parallelism Address allocation scheme for S1 Address allocation scheme for S6

4. Evaluation platform SSD simulator (SSDsim) –Configuration parameters Workloads –Real workloads –Synthetic workloads SLC

5. Evaluation results Optimal priority order of exploiting the parallelism in an SSD 1.Channel-level parallelism 2.Die-level parallelism 3.Plane-level parallelism 4.Chip-level parallelism

6. Analysis of the evaluation results PriorityLevel of parallelism Overlapped execution Required chips in a channel Constraints 1Channel levelMemory operation*, Data transfer Single chipDifferent channel 2Die levelMemory operationSingle chipSame chip, Different die 3Plane levelMemory operationSingle chipSame die, Different plane, Same page, Same command 4Chip levelMemory operationMultiple chipsSame channel, Different chip * Read, program, erase operation