1. Synch 1.1 Synchronous Counters 1 ©Paul Godin Created January 2008

2. Synchronous Counters Asynchronous Counters are problematic for many applications due to glitches caused by the rippling effect of their design. Synchronous Counters help eliminate these glitches by providing a clock pulse to all of the flip-flops at the same time (synchronized). Synchronous Counters can also operate at higher speeds due to the lack of the propagation delays present in the Asynchronous design. Synch 1.2

3. Patterns As with the Asynchronous Counters, a pattern develops when counting in binary. With each flip-flop getting a clock edge from the same source a means of advancing the count must be found within the pattern. LSB MSB Synch 1.3

4. Patterns For the LSB there cannot be any changes; the Flip-Flop must divide the initial clock pulses by 2. ◦ Accomplished by toggling. For the next digit, a toggle is required when the first Flip- Flop is about to go into the low state. LSB MSB Synch 1.4

5. First 2 Stages Look at the state of the input just prior to the clock edge. Synch 1.5

6. Stage 3 The third stage requires more thought. The output of stage 3 toggles high when both stage 1 AND stage 2 are high and about to go low. LSB MSB Synch 1.6

7. Stages 1,2,3 When Q1 AND Q2 are high, stage 3 JK input is high If stages 1 and 2 are high, stage 3 Flip-Flop detects a 1-1 input and toggles. Synch 1.7

8. Additional Stages Every stage after the first 2 is configured the same way: ◦ Use cascaded AND gates to detect the 2 closest least-significant states. Synch 1.8

9. Truncating For the Synchronous counter, truncating can be accomplished in the same manner as with the Asynchronous counter. ◦ Detect the next unwanted state and provide a preset/clear to the asynchronous inputs of the flip-flop. There are better ways of truncating a count with synchronous counters. Synch 1.9

10. Count Direction The count direction can be changed by: ◦ changing between Q/Q’ as the output ◦ changing the configuration of the AND gates to detect the Q/Q’ outputs. Universal counters are available that permit selection of count direction. Synch 1.10

11. Questions 1. Is it possible to have glitches with a full sequence synchronous counter? Explain. 2. What is a disadvantage of Synchronous counters? Synch 1.11

12. END ©Paul R. Godin prgodin @ gmail.com Synch 1.12