1. Counters By Taweesak Reungpeerakul
Chapter 8
Counters
By Taweesak Reungpeerakul
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2. Contents Introduction Asynchronous Counter Synchronous Counter
Up/Down Synchronous Counters
Design of Synchronous Counters
Cascaded Counters
Counter Decoding
Counter Applications
Conclusions
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3. 8.1 Introduction Counting in binary. 0 0 0 0 0 1 0 1 0 0 1 1
1 1 0
1 1 1
LSB changes on every number.
The next bit changes on every fourth number.
The next bit changes on every other number.
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4. 8.1 Introduction (cont.)
Counter can be formed by connecting FFs together
Counter can be categorized into two cases, according to the ways they are clocked !!
Asynchronous counter (ripple counter)
Each FF formed counter do not change their states at the same time
Synchronous counter
Each FF in this counter is clocked concurrently.
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5. 8.2 Asynchronous Counters
Three bit asynchronous counter
In an asynchronous counter, the clock is applied only to the first stage. Subsequent stages derive the clock from the previous stage.
The three-bit asynchronous counter shown is typical. It uses J-K flip-flops in the toggle mode.
CLK K0 J0 Q0 C J1 J2 K1 K2 Q1 Q2
HIGH
Waveforms are on the following slide…
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6. 8.2 Asynchronous Counters (cont.)
Notice that the Q0 output is triggered on the leading edge of the clock signal. The following stage is triggered from Q0. The leading edge of Q0 is equivalent to the trailing edge of Q0. The resulting sequence is that of an 3-bit binary up counter.
CLK Q0 Q1 Q2
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7. 8.2 Asynchronous Counters (cont.)
Propagation delay
Asynchronous counters are sometimes called ripple counters, because the stages do not all change together. For certain applications requiring high clock rates, this is a major disadvantage.
CLK
Notice how delays are cumulative as each stage in a counter is clocked later than the previous stage. Q0 Q1 Q2
Q0 is delayed by 1 propagation delay, Q2 by 2 delays and Q3 by 3 delays.
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8. 8.2 Asynchronous Counters (cont.)
The modulus of a counter is the number of output states it
goes through before returning its self back to zero.
The maximum possible number of states (maximum modulus)
of a counter is 2n
CLK K0 J0 Q0 C J1 J2 K1 K2 Q1 Q2
HIGH
Counter with 3 FFs count from 0-7 and called modulo-8 counter.
Counters can be designed to have a number of states in their
sequences <2n. This type of sequence is called a
truncated sequence.
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9. 8.2 Asynchronous Counters (cont.)
Asynchronous decade counter
This counter uses partial decoding to recycle the count sequence to zero after the 1001 state (modulo-10 counter).
CLK K0 J0 Q0 C J1 J2 K1 K2 Q1 Q2
HIGH J3 K3 Q3
CLR
Use the output of NAND gate
to clear input of the FFs
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10. 8.2 Asynchronous Counters (cont.)
Asynchronous decade counter (cont.)
When Q1 and Q3 are HIGH together, the counter is cleared by a “glitch” on the CLR line.
CLK Q0
Glitch Q1 Q2 Q3
CLR
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Glitch

11. 8.2 Asynchronous Counters (cont.)
The 74LS93A asynchronous counter
The 74LS93A has one independent toggle J-K flip-flop driven by CLK A and three toggle J-K flip-flops that form an asynchronous counter driven by CLK B.
The counter can be extended to form a 4-bit counter by connecting Q0 to the CLK B input. Two inputs are provided that clear the count.
CLK B J0 J1 J2 J3
CLK A C C C C K0 K1 K2 K3
All J and K inputs are connected internally HIGH
RO (1)
RO (2)
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12. 8.3 Synchronous Counters
All flip-flops are clocked together with a common clock pulse.
Trade small propagation delays with more circuitry to control states changes.
Toggle mode
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13. 8.3 Synchronous Counters (cont.)
Timing diagram of 2-bit synchronous counter
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14. 8.3 Synchronous Counters (cont.)
3-bit binary synchronous counter
HIGH Q0
Q0Q1 Q0 Q1 Q2 J0 J1 J2 C C C K0 K1 K2
CLK
Timing diagram of 3-bit synchronous counter
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15. 8.3 Synchronous Counters (cont.)
Analysis of synchronous counters (Tabular technique)
1. Put the counter in an arbitrary state; then determine the inputs for this state.
HIGH Q0
Q0Q1 Q0 Q1 Q2 J0 J1 J2
2. Use the new inputs to determine the next state: Q2 and Q1 will latch and Q0 will toggle. C C C K0 K1 K2
3. Set up the next group of inputs from the current output.
CLK
Outputs
Logic for inputs
Q2 Q1 Q0
J2 = Q0Q1
K2 = Q0Q1
J1 = Q0
K1 = Q0
J0 = 1
K0 = 1 1 1 1 1 1 1
4. Q2 will latch again but both Q1 and Q0 will toggle.
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16. 8.3 Synchronous Counters (cont.)
Analysis of synchronous counters (Tabular technique)
Outputs
Logic for inputs
Q2 Q1 Q0
J2 = Q0Q1
K2 = Q0Q1
J1 = Q0
K1 = Q0
J0 = 1
K0 = 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
At this points all states have been accounted for and the counter is ready to recycle…
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17. 8.3 Synchronous Counters (cont.)
A 4-bit synchronous binary counter
The 4-bit binary counter has one more AND gate than the 3-bit counter just described. The shaded areas show where the AND gate outputs are HIGH causing the next FF to toggle. Q0 Q1 Q2 Q3
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18. 8.3 Synchronous Counters (cont.)
4-bit synchronous decade counter
With some additional logic, a binary counter can be converted to a BCD synchronous decade counter. After reaching the count 1001, the counter recycles to 0000.
This gate detects 1001, and causes FF3 to toggle on the next clock pulse. FF0 toggles on every clock pulse. Thus, the count starts over at 0000. Q3 Q0
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19. 8.3 Synchronous Counters (cont.)
Waveforms for the decade counter:
CLK Q0 Q1 Q2 Q3
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20. 8.3 Synchronous Counters (cont.)
A 4-bit synchronous binary counter in IC form
The 74LS163 is a 4-bit IC synchronous counter with additional features over a basic counter. It has parallel load, a CLR input, two chip enables, and a ripple count output that signals when the count has reached the terminal count.
Data inputs D0 D1 D2 D3
(Ripple Clock Output)
goes high when count to
state 15
CLR
LOAD
ENT
RCO
ENP
CLK
Both enable I/Ps Q0 Q1 Q2 Q3
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Data outputs

21. 8.3 Synchronous Counters (cont.)
CLR
LOAD D0 D1
Data inputs D2 D3
CLK
ENP
ENT Q0 Q1
Data outputs Q2 Q3
RCO
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Count Inhibit
Clear Preset

22. 8.4 Up/Down Synchronous Counters
Counting in either direction (also called a bi-directional counter)
Says if u’d like to design a 3-bit up/down counter
Clock pulse Up Q2 Q1 Q0
Down
Always toggle,
hence J0=K0 =1
Down/ Q1 changes states
when Q0=0
Down/ Q2 changes states
when Q1&Q0=0
Up/ Q2 changes states
when Q1&Q0=1 1 2 3 4 5 6 7
Up/ Q1 changes states
when Q0=1 1 1 1
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23. 8.4 Up/Down Synchronous Counters (cont.)
HIGH
FF0
FF1
FF2 Q2 J0 J1 J2 Q0 Q1
UP/DOWN C C C Q0 Q1 Q2 K0 K1 K2
DOWN
Q0.DOWN
CLK
Basic 3-bit up/down synchronous counter
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24. 8.4 Up/Down Synchronous Counters (cont.)
Data inputs
Data outputs
MAX/MIN
CLK Q0 Q1 Q2 Q3
LOAD
CTEN
RCO
D/U D0 D1 D2 D3 C
CTR DIV 10
74HC190
The 74HC190 is a high speed CMOS synchronous up/down decade counter with parallel load capability. It also has a active LOW ripple clock output (RCO) and a MAX/MIN output when the terminal count is reached.
Data inputs
Data outputs
MAX/MIN
CLK Q0 Q1 Q2 Q3
LOAD
CTEN
RCO
D/U D0 D1 D2 D3 C
CTR DIV 16
74HC191
The 74HC191 has the same inputs and outputs but is a synchronous up/down binary counter.
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25. 8.5 Design of Synchronous Counters
General model of a sequential circuit
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26. 8.5 Design of Synchronous Counters (cont.)
Design procedure for synchronous counters
Step I: State diagram
Step II: Next state table:
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27. 8.5 Design of Synchronous Counters (cont.)
Step III: FF transition table
The J-K transition table lists all combinations of present output (QN) and next output (QN+1) on the left. The inputs that produce that transition are listed on the right.
Each time a flip-flop is clocked, the J and K inputs required for that transition are mapped onto a K-map.
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28. 8.5 Design of Synchronous Counters (cont.)
Step IV: K-maps
Example of mapping procedure
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29. 8.5 Design of Synchronous Counters (cont.)
Step IV: K-maps (cont.)
K-maps for present-state J&K inputs
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30. 8.5 Design of Synchronous Counters (cont.)
Step V: Logic expressions
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31. 8.5 Design of Synchronous Counters (cont.)
Step VI: Counter implementation
FF0
FF1
FF2 Q2 J0 J1 J2 Q0 Q1 C C C Q0 Q1 Q2 K0 K1 K2
CLK
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32. 8.6 Cascaded counters
Cascading is a method of achieving higher-modulus counters. For synchronous IC counters, the next counter is enabled only when the terminal count of the previous stage is reached.
Two cascaded asynchronous counter
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Timing diagram

33. 8.6 Cascaded Counters (cont.)
HIGH
CLK Q0 Q1 Q2 C
Counter 1
Counter 2
CTEN
CTR DIV 16 Q3 TC
fin
fout
Modulus-256 synchronous counter using two cascaded synchronous counters
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34. 8.7 Counter Decoding Question
Decoding is the detection of a binary number and can be done with an AND gate.
Question
1.What number is decoded by this gate?
2. How to modify it in order to provide active-LOW decoding?
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35. 8.7 Counter Decoding (cont.)
Decoding glitches
BCD counter and decoder
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36. 8.7 Counter Decoding (cont.)
Way to eliminate glitches
BCD counter and decoder with strobing
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37. 8.8 Counter Applications
Digital clocks
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38. Typical divide-by-60 Counter
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39. Hours Counter
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40. 8.8 Counter Applications (cont.)
Automobile parking control
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41. 8.9 Conclusions Counters can be implemented in either asynchronous
and synchronous operated form
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