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CYU / CSIE / Yu-Hua Lee / E- 1 數位邏輯 Digital Fundamentals Chapter 9 Counters.

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Presentation on theme: "CYU / CSIE / Yu-Hua Lee / E- 1 數位邏輯 Digital Fundamentals Chapter 9 Counters."— Presentation transcript:

1 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 1 數位邏輯 Digital Fundamentals Chapter 9 Counters

2 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 2 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

3 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 3 Figure 9--1 A 2-bit asynchronous binary counter. Open file F09-01 to verify operation.

4 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 4 Figure 9--2 Timing diagram for the counter of Figure 9-1. As in previous chapters, output waveforms are shown in green.

5 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 5 Figure 9--3 Three-bit asynchronous binary counter and its timing diagram for one cycle. Open file F09-03 to verify operation.

6 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 6 Figure 9--4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.

7 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 7 Figure 9--5 Four-bit asynchronous binary counter and its timing diagram. Open file F09-05 and verify the operation.

8 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 8 Figure 9--6 An asynchronously clocked decade counter with asynchronous recycling.

9 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 9 Figure 9--7 Asynchronously clocked modulus-12 counter with asynchronous recycling.

10 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 10 Figure 9--8 The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.)

11 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 11 Figure 9--9 Two configurations of the 74LS93A asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n states.)

12 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 12 Figure 9--10 74LS93A connected as a modulus-12 counter.

13 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 13 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

14 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 14 Figure 9--11 A 2-bit synchronous binary counter.

15 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 15 Figure 9--12 Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal).

16 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 16 Figure 9--13 Timing diagram for the counter of Figure 9-11.

17 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 17 Figure 9--14 A 3-bit synchronous binary counter. Open file F09-14 to verify the operation.

18 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 18 Figure 9--15 Timing diagram for the counter of Figure 9-14.

19 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 19 Figure 9--16 A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas.

20 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 20 Figure 9--17 A synchronous BCD decade counter. Open file F09-17 to verify operation.

21 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 21 Figure 9--18 Timing diagram for the BCD decade counter (Q 0 is the LSB).

22 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 22 Figure 9--19 The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.)

23 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 23 Figure 9--20 Timing example for a 74HC163.

24 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 24 Figure 9--21 The 74LS160 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.)

25 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 25 Figure 9--22 Timing example for a 74LS160.

26 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 26 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

27 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 27 Figure 9--23 A basic 3-bit up/down synchronous counter. Open file F09-23 to verify operation.

28 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 28 Figure 9--24

29 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 29 Figure 9--25 The 74HC190 up/down synchronous decade counter.

30 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 30 Figure 9--26 Timing example for a 74HC190.

31 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 31 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

32 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 32 Figure 9--27 General clocked sequential circuit.

33 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 33 Figure 9--28 State diagram for a 3-bit Gray code counter.

34 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 34 Figure 9--29 Examples of the mapping procedure for the counter sequence represented in Table 9-7 and Table 9-8.

35 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 35 Figure 9--30 Karnaugh maps for present-state J and K inputs.

36 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 36 Figure 9--31 Three-bit Gray code counter. Open file F09-31 to verify operation.

37 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 37 Figure 9--32

38 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 38 Figure 9--33

39 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 39 Figure 9--34

40 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 40 Figure 9--35 State diagram for a 3-bit up/down Gray code counter.

41 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 41 Figure 9--36 J and K maps for Table 9-11. The UP/DOWN control input, Y, is treated as a fourth variable.

42 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 42 Figure 9--37 Three-bit up/down Gray code counter.

43 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 43 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

44 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 44 Figure 9--38 Two cascaded counters (all J and K inputs are HIGH).

45 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 45 Figure 9--39 Timing diagram for the cascaded counter configuration of Figure 9-38.

46 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 46 Figure 9--40 A modulus-100 counter using two cascaded decade counters.

47 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 47 Figure 9--41 Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide- by-10 and divide-by-100 outputs.

48 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 48 Figure 9--42

49 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 49 Figure 9--43 A divide-by-100 counter using two 74LS160 decade counters.

50 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 50 Figure 9--44 A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D 0 is the LSB in each counter).

51 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 51 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

52 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 52 Figure 9--45 Decoding of state 6 (110). Open file F09-45 to verify operation.

53 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 53 Figure 9--46 A 3-bit counter with active-HIGH decoding of count 2 and count 7. Open file F09-46 to verify operation.

54 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 54 Figure 9--47 A basic decade (BCD) counter and decoder.

55 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 55 Figure 9--48 Outputs with glitches from the decoder in Figure 9-47. Glitch widths are exaggerated for illustration and are usually only a few nanoseconds wide.

56 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 56 Figure 9--49 The basic decade counter and decoder with strobing to eliminate glitches.

57 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 57 Figure 9--50 Strobed decoder outputs for the circuit of Figure 9-49.

58 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 58 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

59 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 59 Figure 9--51 Simplified logic diagram for a 12-hour digital clock. Logic details using specific devices are shown in Figures 9-52 and 9-53.

60 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 60 Figure 9--52 Logic diagram of typical divide-by-60 counter using 74LS160A synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB).

61 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 61 Figure 9--53 Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB.

62 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 62 Figure 9--54 Functional block diagram for parking garage control.

63 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 63 Figure 9--55 Logic diagram for modulus-100 up/down counter for automobile parking control.

64 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 64 Figure 9--56 Parallel-to-serial data conversion logic.

65 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 65 Figure 9--57 Example of parallel-to-serial conversion timing for the circuit in Figure 9-56.

66 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 66 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

67 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 67 Figure 9--58 Example of a failure that affects following counters in a cascaded arrangement.

68 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 68 Figure 9--59 Example of a failure in a cascaded counter with a truncated sequence.

69 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 69 Figure 9--60

70 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 70 Figure 9--61

71 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 71 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

72 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 72 Figure 9--62 The 74HC163 4-bit synchronous counter.

73 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 73 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

74 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 74 Figure 9--63 Combinational mode for active-LOW and active-HIGH outputs. The red lines show the logic paths in each case.

75 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 75 Figure 9--64 Registered mode for active-LOW and active-HIGH outputs. The red lines show the logic paths in each case.

76 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 76 Figure 9--65

77 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 77 數位邏輯 Digital Fundamentals Chapter 9 Counters Digital System Application

78 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 78 Figure 9--66 Traffic light control system block diagram and light sequence.

79 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 79 Figure 9--67 Block diagram of the sequential logic.

80 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 80 Figure 9--68 State diagram showing the 2-bit Gray code sequence.

81 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 81 Figure 9--69 Sequential logic.

82 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 82 Figure 9--70

83 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 83 Figure 9--71

84 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 84 Figure 9--72

85 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 85 Figure 9--73 Comparison of asynchronous and synchronous counters.

86 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 86 Figure 9--74 Note that the labels (names of inputs and outputs) are consistent with text but may differ from the particular manufacturer ’ s data book you are using. The devices shown are functionally the same and pin compatible with the same device types in other available TTL and CMOS IC families.

87 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 87 數位邏輯 Digital Fundamentals Chapter 9 Counters PROBLEMS

88 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 88 Figure 9--75

89 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 89 Figure 9--76

90 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 90 Figure 9--77

91 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 91 Figure 9--78

92 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 92 Figure 9--79

93 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 93 Figure 9--80

94 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 94 Figure 9--81

95 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 95 Figure 9--82

96 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 96 Figure 9--83

97 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 97 Figure 9--84

98 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 98 Figure 9--85

99 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 99 Figure 9--86

100 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 100 Figure 9--87

101 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 101 Figure 9--88

102 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 102 Figure 9--89

103 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 103 Figure 9--90

104 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 104 Figure 9--91

105 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 105 Figure 9--92

106 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 106 Figure 9--93

107 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 107 Figure 9--94

108 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 108 Figure 9--95

109 CYU / CSIE / Yu-Hua Lee / E- mail:yuhualee@cyu.edu.tw 109 Figure 9--96

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