1. EEE2243 Digital System Design Chapter 4: Verilog HDL (Sequential) by Muhazam Mustapha, January 2011

2. Learning Outcome By the end of this chapter, students are expected to be able to: –Design State Machine –Write Verilog State Machine by Boolean Algebra and by Behavior

3. Chapter Content Finite State Machine Controller Design

4. Finite State Machine Vahid §3.3 pg 122

5. Formalism Finite State Machine consists of: –A set of states –A set of inputs –A set of outputs –An initial state –A set of transitions depending on input conditions –An action associated to each state that tells how the output value is computed Finite state machine is used to define sequential circuit behavior 2 types of FSM: Mealy & Moore Vahid pg 126

6. Mealy Machine Output depends on both state and input Input Output State Transition Conditions State Output Computation Input Output

7. Mealy Machine Since input can control output (not only clock input), Mealy machine tends to be asynchronous in nature But the output can be bundled together to finally be controlled by a single clock – thus making it synchronous

8. Moore Machine Output depends only on state State Transition Conditions State Output Computation Input Output

9. Moore Machine Moore machine tends to be synchronous in nature as the state registers are combined together to be controlled by a single clock

10. Capturing FSM Behavior Design of FSM at gate level (in introductory courses) are tedious because we have to manually design the combinational circuit, minimize the state, condition the flip-flop to change, etc At HDL level (intermediate courses), all those are done by software, and the actual hardware is provided by the FPGA –which means in many cases minimization is useless For this chapter, we will do only some mental minimization

11. Capturing FSM Behavior Vahid gives the follows scheme to capture FSM: –List states –Create transitions –Refine FSM: mentally try to figure out if states can be reduce, circuit can be minimized Example and demo: –Oscillator (Vahid page 504, Figure 9.20) –Counter design Vahid pg 129

12. Oscillator Off On 1 clock 0 module Osc(clk); output clk; reg clk; always begin clk <= ~clk; #10; end endmodule Vahid pg 504 module Osc(clk); output clk; reg clk; always begin clk <= 0; #10; clk <= 1; #10; end endmodule D Q Q clk By behavior By Boolean Algebra

13. Counter Counter is a sequential circuit that stores the no. times certain events occur – normally the clock pulses There are a few types of counters, but for our course we will only design synchronous counter with D flip-flop Counters are characterized by the no. of counts it can store –in term of FSM this is called states Counters that store N counts (N states) is called mod N counters

14. Full Counter Mod N counters with N = 2 n (n = no. registers) are called full counters Full counters use all available states that can be provided by the registers Just as the combinational circuits, full counters can also be defined in Verilog as Boolean Algebra or behavioral –effectively there is only one way to define the counter by boolean approach – just as the boolean expression defines it –there are more than one ways to define by behavioral approach

15. 4-Bit Full Counter Boolean Algebra Style Defining counters (or any other FSM) as boolean algebra requires calculations involving excitation table: Current State Next State ABCD 00000001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000

16. 4-Bit Full Counter Boolean Algebra Style We can take the plain excitation equations, or minimize them: 1111 1111 AB CD 1111 1111 AB CD 11 11 11 11 AB CD 11 11 11 11 AB CD

17. 4-Bit Full Counter Boolean Algebra Style The circuit: D Q Q clk D Q Q D Q Q D Q Q DCBA

18. 4-Bit Full Counter Boolean Algebra Style The Verilog code: module FC4Bit(c, clk); input c; output [3:0] clk; reg [3:0] clk; always@(posedge c) begin clk[3] <= ~clk[3]; clk[2] <= ~clk[2]&clk[3] | clk[2]&~clk[3]; clk[1] <= clk[1]&~clk[2] | clk[1]&~clk[3] | ~clk[1]&clk[2]&clk[3]; clk[0] <= clk[0]&~clk[1] | clk[0]&~clk[2] | clk[0]&~clk[3] | ~clk[0]&clk[1]&clk[2]&clk[3]; end endmodule

19. 4-Bit Full Counter Boolean Algebra Style Or Verilog code with keyword wire to structure your code: module FC4Bit(c, clk); input c; output [3:0] clk; reg [3:0] clk; wire AND1, AND2, AND3; wire AND4, AND5, AND6; wire AND7, AND8, AND9; assign AND1 = ~clk[2]&clk[3]; assign AND2 = clk[2]&~clk[3]; assign AND3 = clk[1]&~clk[2]; assign AND4 = clk[1]&~clk[3]; assign AND5 = ~clk[1]&clk[2]&clk[3]; assign AND6 = clk[0]&~clk[1]; assign AND7 = clk[0]&~clk[2]; assign AND8 = clk[0]&~clk[3]; assign AND9 = ~clk[0]&clk[1]&clk[2]&clk[3]; always@(posedge c) begin clk[3] <= ~clk[3]; clk[2] <= AND1|AND2; clk[1] <= AND3|AND4|AND5; clk[0] <= AND6|AND7|AND8|AND9; end endmodule

20. 4-Bit Full Counter Behavioral Style The Verilog code: module FC4Bit(c, clk); input c; output [3:0] clk; reg [3:0] clk; always@(posedge c) case (clk) 0: clk = 1; 1: clk = 2; 2: clk = 3; 3: clk = 4; 4: clk = 5; 5: clk = 6; 6: clk = 7; 7: clk = 8; 8: clk = 9; 9: clk = 10; 10: clk = 11; 11: clk = 12; 12: clk = 13; 13: clk = 14; 14: clk = 15; 15: clk = 0; endcase endmodule module FC4Bit(c, clk); input c; output [3:0] clk; reg [3:0] clk; always@(posedge c) clk <= clk+1; endmodule Or:

21. Partial Counter Mod N counters with N < 2 n (n = no. registers) are called partial counters Partial counters don’t use all available states that can be provided by the registers The counting sequence skips some states in order to produce the required counting mod

22. 3-Bit Partial Counter Behavioral Style 3-bit mod 5 counter with initial value 2 (keyword initial ): module FC4Bit(c, clk); input c; output [2:0] clk; reg [2:0] clk; initial clk <= 2; always@(posedge c) begin if (clk == 6) clk <= 2; else clk <= clk+1; end endmodule Try on your own the Boolean style to write this counter, as well as other ways to write the behavior code

23. Controller Design Vahid §3.3 pg 132

24. Controller By designing FSM as a controller, we get rid of specific Mealy or Moore machine We specify the machine as general construct, then the actual implementation depends on the actual hardware We just specify FSM in a standard architecture Vahid pg 132 Combinational logic S m m N O I clk m-bit state register FSM outputs FSM inputs

25. Controller Steps Vahid pg 133 - modified

26. Controller Design Discussion Vahid slide Want generate sequence 0001, 0011, 1100, 1000, (repeat) –Each value for one clock cycle –Common, e.g., to create pattern in 4 lights, or control magnets of a “stepper motor” 00 0110 11 A B D wxyz=0001wxyz=1000 wxyz=0011wxyz=1100 C Inputs: none; Outputs: w,x,y,z Step 3: Encode states Step 4: Create state table clk State register w x y z FSM outputs n0 s0s1 n1 Step 5: Create combinational circuit w = s1 x = s1s0’ y = s1’s0 z = s1’ n1 = s1 xor s0 n0 = s0’ a Step 1: Create FSM A B D wxyz=0001wxyz=1000 wxyz=0011wxyz=1100 C Inputs: none; Outputs: w,x,y,z Step 2: Create architecture Combinational logic n0 s1s0 n1 clk State register w x y z

27. Controller Design Discussion Book reading session: –Vahid Example 3.10 page 138 (Vahidpg138.jpg) Also read Vahid –Common Mistakes when Capturing FSM, page 142 –FSM and Controller Conventions, page145 Vahid pg 129