1. Registers and Counters by Dr. Amin Danial Asham

2. References  Digital Design 5 th Edition, Morris Mano

3.  Registers are group of FF’s.  Each FF stores a binary bit.  Therefore, n-bits registers has n- FF’s.

4.  4-bits Register.  This register has a clear signal to reset all FF’s.  This register is positive edge trigger.

5.  Shift Register  Data is injected serially in serial input SI into the register with each clock pulse.  Sine the data is shifted inside the register it comes out serially as well from serial output SO SI SO

7.  Ripple Counters (Asynchronous) with JK-FF’s Two-bit asynchronous counter  Each FF is connected as a toggle FF triggered by the previous FF. That is: Q0 is complemented each time clock goes from 1 to 0. Q1 is complemented each time Q0 goes from 1 to 0. That means the trigger is propagated through the counter as a ripple fashion from the clock to the most significant bit through FF’s.

8.  Ripple Counters (Asynchronous) with D-FF’s

9.  Ripple Counters (Asynchronous) with T-FF’s

10.  2-bits Ripple countdown counter. 32 10 3  2-bits ripple count down counter which counter from 3 to 0  All FF’s are positive edge trigger.  The polarity of the clock is essential for ripple counter counter

11.  3 -BCD Ripple Counter (0-999)  Noting that BCD counters here are triggered by the negative edge.

12.  Synchronous counters  A FF in any position is complemented if all the lower significant bits are all 1’a.  When count enable is 0 all J’s and K’s are zeros and hence the clock does not affect the counter state.  The polarity of the clock is not essential for synchronous counters

13.  Up-Down Binary Counter  When the Up enable signal is 1 the counter acts as count-up counter. o A FF in any position is complemented if all the lower significant bits are all 1’a.  When the Down enable signal is 1 and UP signal is 0 the counter acts as count-Down counter. o A FF in any position is complemented if all the lower significant bits are all 0’a.

14.  Up-Down Binary Counter (continue) 0 1 23 0 3 2 10 Logic 1

15. Thanks