1. 1 Successive Approximation Analog-to- Digital Conversion at Video Rates 指導教授 ：汪輝明 學 生：陳柏宏

2. 2 Outline Abstract Introduction The System D/A Conversion The Successive Approximation Register Conclusions

3. 3 Abstract This paper reports preliminary work on successive approximation analog-to-digital converters operating in the video speed range. Details of operation of the eight and ten bit digital-to-analog (D/A) converters are presented, with a description of the function of the complementary successive approximation registers.

4. 4 Introduction This paper describes preliminary work carried out in an effort to achieve low-cost video speed analog-to-digital (ADC) converters using successive approximation techniques 。 The emphasis in this program has been on the achievement of 8-bit ADC’s with a sample rate of 15 MHz and 10-bit systems capable of sampling at 6 MHz 。

5. 5 The System Fig.1 shows the breakdown of the successive approximation A/D converter function into circuit blocks.

6. 6 The System

7. 7 The chief advantage of successive approximation compared with the parallel technique are the (i) significant reduction in hardware. (ii) simplified drive requirements. (iii) low power consumption. Need only some 25 percent more chip area then the 8-bit parts and a speed compromise in successive approximation.

8. 8 D/A Conversion The digital-to-analog conversion technique is based on an array of nominally equal current source (Fig. 2).The diagram shows this general concept as applied to the 8-bit digital-to- analog converter.

9. 9 D/A Conversion Both 8- and 10-bit DAC’s use an identical interstage current divider, show in Fig.3

10. 10 D/A Conversion The division is at one sixteenth of full scale on the 8-bit part, and divides the current contribution from the LSB group by 16. In the 10-bit part, the division is at 1/32 of full scale and, again, is required to divide the LSB group current by 16. The proof of the current division relationship is straightforward and result is

11. 11

12. 12 D/A Conversion This equation indicates that the contribution to I out of I M and I L is in the relation (n+1) :1 and is independent of R and R L.Hence, if the interstage divider has a ratio of 15:1,I L contributes proportionately 1/16 of I out, while I M contributes 15/16. The divider networks consist of eight equal resistors each, three in series and five in parallel, providing an accurate 15 to 1 ratio, independent of process or temperature variations.

13. 13 D/A Conversion Fig.4 show the 10-bit D/A converter chip in basic form, the functional areas on the chip are the voltage reference, the reference amplifier, and the DAC array.

14. 14 D/A Conversion Fig. 5 shows the full scale settling time of the current output into a 50 Ω oscilloscope input. This photograph was taken on the 8-bit DAC; the 10-bit settling performance is very similar.

15. 15 D/A Conversion The results obtained are 5 ns settling time for 8-bit parts and 12 ns for the 10-bit devices, with estimated errors of measurement of ±1/2 ns and ± 1 ns, respectively. Individual switches operate at 1 ns 10 percent to 90 percent rise/fall times, with a current of 2.5 mA in the 4μ×10μ emitter transistor switches. Output “glitch” content is very low, about 80ps ． V in a 1V full scale output (Fig. 6).

16. 16 D/A Conversion Both DAC’s operate from +5V, -5.2V rails, with power dissipation of 400 mW for 8-bit device and 500 mW for the 10 bit. Chip sizes are 1.8 mm x 1.5 mm (8 bit) and 2.5 mm x 1.7 mm (10 bit). At the 10-bit level most devices have ±1/2 LSB differential linearity, and selections can be made for ±1 LSB or ±1/2 LSB absolute linearity. Most functional 8-bit parts are ±1/2 LSB for both differential and absolute linearities, with selections available for ±1/4 LSB.

17. 17 The Successive Approximation Register The SAR block diagram (Fig. 9) shows the main functions of the device.

18. 18 The Successive Approximation Register The logic used is based on ECL with reduced logic swings internal to the chip. Extensive use is made of current sterring logic, illustrate in Fig. 10

19. 19 The Successive Approximation Register Fig. 11 shows the 8-bit successive approximation register. The chip consist of a central shift register with, also on the chip are the D/A latches, and a separate output latch set, again using multilevel logic. A total of nine system clock periods is needed for the 8-bit part and eleven for the 10-bit part. Chip size are 3.6mm x 2.2mm (8-bit) and 4.2mm x 2.2mm, and power dissipations are 450 mW and 550 mW, respectively.

20. 20 The Successive Approximation Register Using one of the D/A converters described, the successive approximation register has been operated up to 107MHz clock rate and is capable of reaching the 135 MHz target for an 8-bit 15 MHz sample rate ADC. Fig. 12 shows the DAC progressively shifting to the “all high” state.

21. 21 The Successive Approximation Register D/A latch command data are received by the SAR chip from the comparator, which compares the DAC output with the incoming analog signal. The comparator may be on-chip, or may be a separate high-speed ECL part. An approximation time allocation budget is show in Table Ι, allowing the full-scale settling time for each bit.

22. 22 Conclusion Glitch levels on the DAC’s are less then 80 ps ． V and do not significantly interfere with the analog-to-digital conversion process. Successive approximation analog-to-digital conversion has been demonstrated at high speed and it is hoped that this will shortly lead to the production of a two-chip video speed A/D converter with minimal drive requirements, low power consumption, and low cost.