1. CPEN 315 - Digital System Design
Digital Circuit Verification
Hardware Descriptive Language
Verilog
C. Gerousis
© Logic and Computer Design Fundamentals, 3rd Ed., Mano
Prentice Hall

2. Overview Behavioral vs. Structural Description
Hardware Descriptive Language (HDL)
Behavioral vs. Structural Description
Gate-Level Description of a simple circuit
Model Abstractions in Verilog
User Defined Primitives (UDPs)
HDL Examples

3. Hardware Descriptive Language (HDL)
HDL languages resemble programming languages,
but are specifically oriented to describing hardware
structures and behavior.
Uses of HDLs:
– They provide alternative to schematics.
– They can represent Boolean equations, truth tables and
complex operations.
In top-down design, a very high description of an
entire system can be precisely specified using an HDL.

4. HDL (continued) Most popular HDLs are
– VHDL (VHSIC (Very High Speed Integrated Circuits)
HDL – Developed for the U. S. DOD.
– Verilog® – Developed by Gateway Design Automation,
which was bought by Cadence® Design Systems.
Verilog represents circuits at a level closer to the
physical hardware.
Language standards are defined, approved and published
by the IEEE.

5. Behavioral vs. Structural Description
Behavioral Description
More like high level software language
Easy to read and understand
In the early stage of design to test the correctness of functionality of the design
Structural Description
Less readable
Like gate level netlist
In the late stage of the design, used to generate netlist.

6. HDL Example 1 //HDL Example 1 //--------------------------
//Gate-Level Description of a simple circuit
module smpl_circuit(A,B,C,x,y); // building block
input A,B,C; // input port
output x,y; // output port
wire e;
and g1(e,A,B); // AND gate (output, inputs)
not g2(y, C);
or g3(x,e,y);
endmodule
Draw the simple circuit

7. Model Abstractions in Verilog
Previous Example is a “netlist”
– Contains enough information to construct in lab
– Structural Model
– Commonly “Lowest” level of abstraction
RTL (register transfer language) Level
– Composed of Boolean Expressions and Registers
– Can be Automatically Synthesized to a netlist
Behavioral Level
– High-level that only Describe Functionality
– Automatic Behavioral Synthesis Tools do Exist

8. User Defined Primitives (UDPs)
• Keywords and, or, not, xor, etc. are System
Primitives
• Can Define your Own Primitives (UDPs)
• Can do this in a variety of ways including Truth
Tables
• Instead of module/endmodule use the keywords
primitive/endprimitive
• Only one output and must be listed first
• Keywords table and endtable used
• Input values listed in order
• Output is always last entry

9. HDL Example 2 //HDL Example 2 //User defined primitive(UDP)
primitive crctp (x,A,B,C); // user defined
output x;
input A,B,C;
//Truth table for x(A,B,C) = Minterms ( ? )
table // truth table
// A B C : x (Note that this is only a comment)
: 1;
: 0;
: 1;
: 0;
: 1;
: 0;
: 1;
: 1;
endtable
endprimitive

10. HDL Example 2 (continued)
module declare_crctp;
reg x,y,z;
wire w;
crctp (w,z,y,z); // produces a circuit that implements
endmodule // w (x,y,z) = S(0, 2, 4, 6 ,7)

11. HDL Example 3 //HDL Example 3 //------------------------------
//Circuit specified with Boolean equations
module circuit_bln (x,y,A,B,C,D);
input A,B,C,D;
output x,y;
assign x = A | (B & C) | (~B & C); //
assign y = (~B & C) | (B & ~C & ~D); //
endmodule

12. 4-bit Adder: Bottom-Up Hierarchical Structure
Half-Adder
2. Full-Adder
3. 4-bit Adder

13. 4-bit Adder: Verilog Description
//HDL Example 4 //
//Gate-level hierarchical description of 4-bit adder
// Description of half adder
module halfadder (S,C,x,y);
input x,y;
output S,C;
//Instantiate primitive gates
xor (S,x,y);
and (C,x,y);
endmodule

14. 4-bit Adder: Verilog (continued)
//Description of the full adder
module fulladder (S,C,x,y,z);
input x,y,z;
output S,C;
wire S1,D1,D2; //Outputs of first XOR and two AND gates
//Instantiate the halfadder
halfadder HA1 (S1,D1,x,y),
HA2 (S,D2,S1,z);
or g1(C,D2,D1);
endmodule S1 D1 D2

15. 4-bit Adder: Verilog (continued)
//Description of 4-bit adder
module _4bit_adder (S,C4,A,B,C0);
input [3:0] A,B; // Input vectors A, B with bits 0 through 3
input C0;
output [3:0] S;
output C4;
wire C1,C2,C3; //Intermediate carries
//Instantiate the fulladder
fulladder FA0 (S[0],C1,A[0],B[0],C0),
FA1 (S[1],C2,A[1],B[1],C1),
FA2 (S[2],C3,A[2],B[2],C2),
FA3 (S[3],C4,A[3],B[3],C3);
endmodule

16. 4-bit Adder: Verilog (continued)
`timescale 1 ps / 1 ps
module testbed();
reg c_in;
reg [3:0] y;
reg [3:0] x;
wire c_out;
wire [3:0]sum;
FourBitAdder A1(sum, c_out, x, y, c_in);
initial
begin //SIGNAL x
x = 4'b1001;
#25000
x = 4'b0001; ;
end

17. 4-bit Adder: Verilog (Final)
initial
begin //SIGNAL y
y = 4'b0001;
#25000
y = 4'b0010; ;
end
begin //SIGNAL c_in
c_in = 1'b0;
#100000
c_in = 1'b1;
# $finish;
endmodule