1. eSilicon Confidential IP Partner Selection November, 2000

2. 2 eSilicon Confidential Quality Function Deployment (QFD) A systematic way to make key decisions objectively with business goals in mind. Establish the key attributes for decision making. Determine the measuring criteria & system. The rating system is 1=poor, 2=below average, 3=average, 4=good, 5=excellent. Team Assessment on each attribute. Consensus should be reached by the team on each rating. The decision will be based on the overall score among different options.

3. 3 eSilicon Confidential Selection Criteria Business Attributes Company Track Record - H Established Customer Base – H Foundry Certified – H Business & Cost Model – H Support Model – H Partnership Motivation – M R&D Spending – M Product or Technology Focus – M Resources & Bandwidth – M Priority decides attr. weighting. H – High, M – Medium, L – Low. Technical Attribute Target Applications - H Appl. Domain Knowledge - H IP Design Process – H for analog IP Qualification Process – H IP Quality Standard - H Documentation - H Model Availability - H Model Accuracy – H System Integration Support – H Test Strategy - H Strategy & Roadmap - M

4. 4 eSilicon Confidential What’s Important to eSilicon Access to high-quality, silicon-proven IP cores. Engage in a cost-effective biz model among customer, IP supplier, & eSilicon. Up-front License Fee vs. Royalties The IP partner has a good strategy & roadmap. The IP partner should bring excellent engineering support to mutual customers. The partner is willing to share business risks & grow with eSilicon together.

5. 5 eSilicon Confidential What’s Important to IP Partner Provide the channel to proliferate the IP cores. Reduce the Sales cycle & support cost. Establish scalable business. Risk sharing. The latest trend is that 3 rd party IP & Design service suppliers are converging in specific vertical segments. Without IP cores, DS companies could not win the business from ASIC suppliers. 3 rd party IP suppliers need to leverage services to reduce Sales cycle & ramp-up revenues.

6. 6 eSilicon Confidential What’s Important to Mutual Customers Risk buffer.

7. 7 eSilicon Confidential CPU Cores Performance vs. Gate Count/Size vs. Low Power Re-Configurability – Instruction Set, Peripherals, Software Embedded Software Support – RTOS, Compiler, Debugger, Device Drivers Bus Architecture Test Methodology - EJTAG DSP Option Roadmap – 16-bit vs. 32-bit vs. 64-bit vs. 128-bit

8. 8 eSilicon Confidential Memories SRAM, REG File, FIFO, ROM, DRAM, NVM, CAM Compiler & Model Creation Synchronous Single, Dual, Multi-Ports Performance vs. Core Size vs. Power Consumption Test Methodology - BIST

9. 9 eSilicon Confidential Analog IP PLL, DAC, ADC PLL – Frequency & Jitter C/HDL Models for System Validation Test Methodology