1. March 2002, JINR Dubna1 A new   e  experiment at PSI For the MUEGAMMA collaboration Stefan Ritt (Paul Scherrer Institute, Switzerland) Introduction Experimental Technique New Electronics Current status

2. March 2002, JINR Dubna2 Physics Motivation SUSY theories generically predict LFV LFV forbidden by Standard Model Processes like  +  e +  are not “contaminated” by SM processes and therefore very clean Discovered oscillations are expected to enhance LFV rate The search for  +  e +  is therefore a promising field to find physics beyond the SM SUSY theories generically predict LFV LFV forbidden by Standard Model Processes like  +  e +  are not “contaminated” by SM processes and therefore very clean Discovered oscillations are expected to enhance LFV rate The search for  +  e +  is therefore a promising field to find physics beyond the SM

3. March 2002, JINR Dubna3 Prediction from SUSY SU(5) This experiment Current experimental bound 2) f t (M)=2.4  >0 M l =50GeV 1) 1)J. Hisano et al., Phys. Lett. B391 (1997) 341 2)MEGA collaboration, hep-ex/9905013

4. March 2002, JINR Dubna4 Connection with oscillations 1) 1)J. Hisano and D. Nomura, Phys. Rev. D59 (1999) 116005 2)MEGA collaboration, hep-ex/9905013 2) This experiment

5. March 2002, JINR Dubna5 Previous  +  e +  Experiments PlaceYearUpper limitAuthor SIN (PSI), Switzerland 1977< 1.0  10 -9 A. Van der Schaaf et al. TRIUMF, Canada1977< 3.6  10 -9 P. Depommier et al. LANL, USA1979 < 1.7  10 -10 W.W. Kinnison et al. LANL, USA1986< 4.9  10 -11 R.D. Bolton et al. LANL, USA1999< 1.2  10 -11 MEGA Collab., M.L. Brooks et al. New experiment: 10 -14 at PSI Letter of Intend 1998 Proposal 1999, approved May 1999 New experiment: 10 -14 at PSI Letter of Intend 1998 Proposal 1999, approved May 1999

6. March 2002, JINR Dubna6 MEG Collaboration InstituteCountryMain Resp.HeadScientistsStudents ICEPP, Univ. of TokyoJapanLXe CalorimeterT. Mori122 Waseda UniversityJapanCryogenicsT. Doke52 INFN, PisaItaly e + counter, trigger, M.C. C. Bemporad43 IPNS, KEK, TsukubaJapan Supercoducting Solenoid A. Maki5- PSISwitzerland Drift Chamber, Beamline, DAQ S. Ritt4- BINP, NovosibirskRussia LXe Tests and Purification B. Khazin4- Nagoya UniversityJapanCryogenicsK. Masuda1- 35 7

7. March 2002, JINR Dubna7 Experimental Method Stopped  beam of 10 8 s -1, 100% duty factor Liquid Xe calorimeter for  detection Solenoidal magnetic spectrometer with gradient field Radial drift chambers for e + momentum determination Timing counter for e + Stopped  beam of 10 8 s -1, 100% duty factor Liquid Xe calorimeter for  detection Solenoidal magnetic spectrometer with gradient field Radial drift chambers for e + momentum determination Timing counter for e + E e = 52.8 MeV Kinematics  e  = 180° E g = 52.8 MeV e  

8. March 2002, JINR Dubna8 Signal and Background  +  e +  signal very clear –E  = E e+ = 52.8 MeV –   e+ = 180° –e + and  in time Background –Radiative  + decays –Accidental overlap Detector Requirements –Excellent energy resolution –Excellent timing resolution –Good angular resolution ee e  e   ee  e    e  e 

9. March 2002, JINR Dubna9   e  Signature  e  E e,E  = 52.8MeV  e  E e,E  < 52.8MeV X = E e /52.8MeV Y = E  /52.8MeV

10. March 2002, JINR Dubna10 Sensitivity and Background Rate BR(  e  ) = (N  T  /4   e    sel ) -1 = 0.94  10 -14 NN 1  10 8 T2.2  10 7 s (~50 weeks)  /4  0.09 ee 0.95  0.7  sel 0.8 FWHM EeEe 0.7% EE 1.4%  e  12 mrad tete 150 ps Prompt Background B pr  10 -17 Accidental BackgroundB acc   E e  t e  (  E  ) 2 (  e  ) 2  5  10 -15

11. March 2002, JINR Dubna11 Paul Scherrer Institute Experimental Hall

12. March 2002, JINR Dubna12 Experimental Hall

13. March 2002, JINR Dubna13 Sindrum II @ PSI  - Ti  e - Ti : Oct. 2000 (50d) beam time: 90% C.L. limit: 6.1 10 -13 B ue =4 10 -12

14. March 2002, JINR Dubna14  E5 Beam Line 10 8  /s on 5  5 mm 2 Neutron background measured in 1998 Two Beam tests in 2002 10 8  /s on 5  5 mm 2 Neutron background measured in 1998 Two Beam tests in 2002

15. March 2002, JINR Dubna15 Detector

16. March 2002, JINR Dubna16 LXe Calorimeter ~800l liquid Xe (3t) ~800 PMTs immersed in LXe Only scintillation light detected Fast response (45 ns decay time) High light output (70% of NaI(Tl)) 1) High uniformity compared with segmented calorimeters High channel occupancy will be accommodated by special trigger scheme ~800l liquid Xe (3t) ~800 PMTs immersed in LXe Only scintillation light detected Fast response (45 ns decay time) High light output (70% of NaI(Tl)) 1) High uniformity compared with segmented calorimeters High channel occupancy will be accommodated by special trigger scheme 1) T. Doke and K. Masuda, NIM A 420 (1999) 62

17. March 2002, JINR Dubna17  Response Signal is distributed over many PMTs in most cases Weighted mean of PMTs on the front face   x ~ 4mm FWHM Broadness of distribution   z ~ 16mm FWHM Timing resolution   t ~ 100ps FWHM Energy resolution ~ 1.4% FWHM depends on light attenuation in LXe Signal is distributed over many PMTs in most cases Weighted mean of PMTs on the front face   x ~ 4mm FWHM Broadness of distribution   z ~ 16mm FWHM Timing resolution   t ~ 100ps FWHM Energy resolution ~ 1.4% FWHM depends on light attenuation in LXe x z

18. March 2002, JINR Dubna18 Calorimeter Prototypes 32 PMTs, 2.3 l LXe Tested with radioactive sources 51 Cr, 137 Cs, 54 Mn, 88 Y Extrapolated resolutions at 52.8 MeV in agreement with quoted numbers “Small”“Large” Measure resolutions with 40 MeV photon beam at ETL, Tsukuba, Japan

19. March 2002, JINR Dubna19 Large Prototype Currently largest LXe detector in the world (224 PMTs, 150l), Contains all critical parts of final detector

20. March 2002, JINR Dubna20 Positron Spectrometer Homogeneous Field Gradient Field (COnstant-Bending-RAdius) e + from  +  e +  Ultra-Thin (~3g/cm2) superconducting solenoid with 1.2 T field Ultra-Thin (~3g/cm2) superconducting solenoid with 1.2 T field

21. March 2002, JINR Dubna21 Drift Chamber 16 radial chambers with 20 wires each Staggered cells measure both position and time He – C 2 H 6 gas to reduce multiple scattering Vernier pattern to determine z coordinate 16 radial chambers with 20 wires each Staggered cells measure both position and time He – C 2 H 6 gas to reduce multiple scattering Vernier pattern to determine z coordinate

22. March 2002, JINR Dubna22 Prototype Test at PSI 0, 0.6, 0.8, 1T field 3 tilting angles Chamber ok, electronics needs improvement 0, 0.6, 0.8, 1T field 3 tilting angles Chamber ok, electronics needs improvement

23. March 2002, JINR Dubna23 Positron timing counter Aimed resolution ~100ps FWHM Beam tests at KEK in July 1999 Taken over by Pisa group Tests with cosmic  confirmed 100ps FWHM Aimed resolution ~100ps FWHM Beam tests at KEK in July 1999 Taken over by Pisa group Tests with cosmic  confirmed 100ps FWHM http://meg.psi.ch/ subprojects/tcount/ http://meg.psi.ch/ subprojects/tcount/

24. March 2002, JINR Dubna24 Trigger Requirements  Beam rate10 8 s -1  Fast LXe energy sum > 45MeV2  10 3 s -1   interaction point  e + hit point in timing counter  time correlation  – e + 200 s -1  angular corrlation  – e + 20 s -1  Beam rate10 8 s -1  Fast LXe energy sum > 45MeV2  10 3 s -1   interaction point  e + hit point in timing counter  time correlation  – e + 200 s -1  angular corrlation  – e + 20 s -1 E e = 52.8 MeV Kinematics  e  = 180° E g = 52.8 MeV e   M.C. Total ~800 PMTs Common noise contributes significantly to analog sum AC coupling  Baseline drift How to evaluate  of shower center? Total ~800 PMTs Common noise contributes significantly to analog sum AC coupling  Baseline drift How to evaluate  of shower center?

25. March 2002, JINR Dubna25 Digital Trigger VME Interface (Cypress) 3.3V 2.5V FADC LVDS FPGA SRAM FADC LVDS FPGA SRAM VME Interface (Cypress) 3.3V 2.5V LVDS FPGA SRAM LVDS FPGA SRAM LVDS 8 channels LVDS 8 channels clck, clear 48 bits output LVDS 10bit / 100MHz

26. March 2002, JINR Dubna26 Baseline Subtraction Latch Baseline Subtraction Latch 10 bit 100 MHz Clock    - + <thr  + - Baseline Register Uses ~120 out of 5000 logic cells  8 channels/FPGA use 20% of chip Uses ~120 out of 5000 logic cells  8 channels/FPGA use 20% of chip Baseline subtracted signal LUT 10x10 Calibrated and linearized signal

27. March 2002, JINR Dubna27 QT Algorithm original waveform smoothed and differentiated (Difference Of Samples) Threshold in DOS Region for pedestal evaluation integration area t Inspired by H1 Fast Track Trigger (A. Schnöning) Difference of Samples (= 1 st derivation) Hit region defined when DOS is above threshold Integration of original signal in hit region Pedestal evaluated in region before hit Time interpolated using maximum value and two neighbor values in LUT  1ns resolution for 10ns sampling time Inspired by H1 Fast Track Trigger (A. Schnöning) Difference of Samples (= 1 st derivation) Hit region defined when DOS is above threshold Integration of original signal in hit region Pedestal evaluated in region before hit Time interpolated using maximum value and two neighbor values in LUT  1ns resolution for 10ns sampling time

28. March 2002, JINR Dubna28 Trigger latency BS    Max...... T[ns] 0 50 100 110 120..200 220 230 >45MeV   e+ AND 10 stages = 1024 chn... ADC...... Inter-board communication: 120 ns Total latency: 350 ns

29. March 2002, JINR Dubna29 Prototype board ADC Signal- Generator DAC FPGA

30. March 2002, JINR Dubna30 DAQ Requirements n E[MeV] 50 51 52 ee Michel edge t PMT sum e    e    e  51.5 MeV 0.511 MeV  ’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm) Timely separated  ’s need waveform digitizing > 300 MHz If waveform digitizing gives timing <100ps, no TDCs are needed  ’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm) Timely separated  ’s need waveform digitizing > 300 MHz If waveform digitizing gives timing <100ps, no TDCs are needed ~100ns

31. March 2002, JINR Dubna31  Domino Sampling Chip 0.5 – 1.2 GHz sampling speed 128 sampling cells Readout at 5 MHz, 12 bit ~ 100 CHF/channel Needed: 2.5 GHz sampling speed Circular domino wave 1024 sampling cells 40 MHz readout < 100ps accuracy C. Brönnimann et al., NIM A420 (1999) 264

32. March 2002, JINR Dubna32 Domino Ring Sampler (DRS) Free running domino wave, stopped with trigger Sampling speed 2 GHz (500ps/bin) Readout 40 MHz 12 bit 1024 bins  150ns waveform + 350ns delay Free running domino wave, stopped with trigger Sampling speed 2 GHz (500ps/bin) Readout 40 MHz 12 bit 1024 bins  150ns waveform + 350ns delay input

33. March 2002, JINR Dubna33 DAQ Board 8 inputs trigger gate FADC 3 state switches FPGA SRAM shift register 9 channels  1024 bins / 40 MHz = 230  s  acceptable dead time Zero suppression in FPGA QT Algorithm in FPGA (store waveform if multi-hit) Costs per channel: ~25$ (board) + 6$ (chip) 9 channels  1024 bins / 40 MHz = 230  s  acceptable dead time Zero suppression in FPGA QT Algorithm in FPGA (store waveform if multi-hit) Costs per channel: ~25$ (board) + 6$ (chip) 40 MHz 12 bit VME Interface (Cypress) 3.3V 2.5V 8 channel DRS Trigger Input Board inter-connect FPGA SRAM FADC 8 channel DRS 8 channel DRS FADC 8 channel DRS Trigger BUS (2 nd level tr.)

34. March 2002, JINR Dubna34 “Redefinition” of DAQ ConventionalNew AC couplingBaseline subtraction Const. Fract. Discriminator DOS – Zero crossing ADCNumerical Integration TDC Bin interpolation (LUT) Waveform Fitting Scaler (250 MHz)Scaler (50 MHz) OscilloscopeWaveform sampling 400 US$ / channel50 US$ / channel TDC Disc. ADC Scaler Scope FADC FPGA SRAM DSC ~GHz 100 MHz

35. March 2002, JINR Dubna35 Cryogenics Design

36. March 2002, JINR Dubna36 New slow control system ADuC812 / C8051F000 Micro controllers with 8x12 bit ADC, 2x12 bit DAC RS485 bus over flat ribbon cable Powered through bus Costs ~30$ Piggy back board ADuC812 / C8051F000 Micro controllers with 8x12 bit ADC, 2x12 bit DAC RS485 bus over flat ribbon cable Powered through bus Costs ~30$ Piggy back board Generic node

37. March 2002, JINR Dubna37 2 versions Generic node with signal conditioning Sub-master with power supply and PC connection (Parallel Port, USB planned) Integration on sensors, in crates RS232 node planned BUS Oriented Crate Oriented 19” crate with custom backplane Generic node as piggy-back Cards for analog IO / digital IO / °C / 220V crate connects to parallel port (USB)

38. March 2002, JINR Dubna38 Midas Slow Control Bus 256 nodes, 65536 with one level of repeaters Bus length ~500m opto-isolated Boards for voltage, current, thermo couples, TTL IO, 220V output Readout speed: 0.3s for 1000 channels C library, command-line utility, Midas driver, LabView driver Nodes are “self-documenting” Configuration parameters in EEPROM on node Node CPU can operate autonomously for interlock and regulation (PID) tasks (C programmable) Nodes can be reprogrammed over network http://midas.psi.ch/mscb 256 nodes, 65536 with one level of repeaters Bus length ~500m opto-isolated Boards for voltage, current, thermo couples, TTL IO, 220V output Readout speed: 0.3s for 1000 channels C library, command-line utility, Midas driver, LabView driver Nodes are “self-documenting” Configuration parameters in EEPROM on node Node CPU can operate autonomously for interlock and regulation (PID) tasks (C programmable) Nodes can be reprogrammed over network http://midas.psi.ch/mscb

39. March 2002, JINR Dubna39 Time Table 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 PlanningR & DAssemblyData Taking now Conclusions Preparations are going well in all areas of the experiment Innovative technologies developed useful for other experiments Next major milestone: Large prototype test in Tsukuba spring 2002 Preparations are going well in all areas of the experiment Innovative technologies developed useful for other experiments Next major milestone: Large prototype test in Tsukuba spring 2002 http://meg.psi.ch