1. Company LOGO DKT 122/3 DIGITAL SYSTEM 1 WEEK #12 LATCHES & FLIP-FLOPS

2.  Latches & Flip-Flops  Differences between Latches and Flip-Flops  Types of Latches and Flip-Flops  Edge-Triggered Flip-Flops  Flip-Flop Operating Characteristics Topic Outlines

3.  Latches and flip-flops are the basic single-bit memory elements used to build sequential circuit with one or two inputs/outputs, designed using individual logic gates and feedback loops. Introduction

4.  Latches  The output of a latch depends on its current inputs and on its previous output and its change of state can happen at any time when its inputs change.  Flip-Flops  The output of a flip-flop also depends on current inputs and its previous output but the change of state occurs at specific times determined by a clock input. Differences between Latches and Flip-Flops Latches & Flip-Flops

5.  Latches  S-R (SET-RESET) Latch  Gated S-R Latch  Gated D-Latch  Flip-Flops  Edge-Triggered S-R Flip-Flop  Edge-Triggered D Flip-Flop  Edge-Triggered J-K Flip-Flop Types of Latches and Flip-Flops Latches & Flip-Flops

6.  Type of temporary storage device that has 2 stable (bi-stable) states  Similar to flip-flop – the outputs are connected back to opposite inputs  Main difference from flip-flop is the method used for changing their state  Types: S-R latch, Gated/Enabled S-R latch and Gated D latch Latches

7. Active-HIGH input S-R Latch Active-LOW input S-R Latch S-R (SET-RESET) Latch Latches

8. S-R Latch Logic symbols Latches

9. Negative-OR equivalent of the NAND gate S-R latch S-R Latch Latches

10. Truth table for an active-LOW input S-R latch S-R Latch Latches Question: What is the truth table for an active-HIGH input S-R latch ?

11. The three modes of basic latch operation SET RESET no-change & the invalid condition S-R Latch

12. Waveforms Assume that Q is initially LOW S-R Latch Latches

13.  A gate input is added to the S-R latch to make the latch synchronous.  In order for the set and reset inputs to change the latch, the gate input must be active (HIGH/Enable).  When the gate input is low, the latch remains in the hold condition. Gated S-R Latch Latches

14. Gated S-R Latch Latches

15. SRGQQ’Comment 000QQ’Hold 100QQ’Hold 010QQ’Hold 110QQ’Hold 001QQ’Hold 10110Set 01101Reset 11100Not allowed Gated S-R Latch Truth-table Latches

16. 1 2 3 45 Gated S-R Latch Waveform Latches

17. 1 2 3 45 Gated S-R Latch Waveform Latches set reset set resetset

18. Gated S-R Latch Application S-R latch is used to eliminate switch contact bounce Latches

19.  The D (data) latch has a single input that is used to set and to reset the flip-flop.  When the gate is high, the Q output will follow the D input.  When the gate is low, the Q output will hold. Gated D Latch (74LS75) Latches

20. Gated D Latch (74LS75) Latches

21. The output follows the input when the gate is high but is in a hold when the gate is low. Gated D Latch (74LS75) Waveform Latches

22.  Flip-flops are synchronous devices  Synchronous means that the output changes state only at a specified point on the triggering input called the clock (CLK)  An edge-triggered flip-flop changes state either at the positive edge (rising edge) or at the negative edge (falling edge)  Three types of edge-triggered flip-flops:  S-R Flip-Flops  D Flip-Flops  J-K Flip-Flops Flip-Flops

23. Edge-triggered flip-flop logic Positive edge- triggered Negative edge- triggered (bubble at C input) Flip-Flops

24. Clock signals and synchronous sequential circuits A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals. Rising edges of the clock (Positive-edge triggered) Falling edges of the clock (Negative-edge triggered) Clock signal Clock Cycle Time 1 0 Flip-Flops

25. Edge-triggered S-R Flip-Flop The basic of S-R flip-flop consist of 2 NOR gates with the outputs cross-coupled to the inputs Cross-NOR S-R Flip-Flop Flip-Flops

26. Note: Flip-flop cannot change state except on the triggering edge of a clock pulse. When S=R=1, invalid condition exists Edge-triggered S-R Flip-Flop Flip-Flops

27. INPUTSOUTPUTS COMMENTS SRCLKQQ 00XQ0Q0 Q0Q0 No change (Hold condition) 01  01RESET 10  10SET 11  ??Invalid  = clock transition LOW to HIGH X = irrelevant (“don’t care”) Q 0 = output level prior to clock transition Edge-triggered S-R Flip-Flop(+ve edge) -ve edge ? Flip-Flops

28.  Addition of an inverter to an S-R flip-flop creates a basic D flip-flop Edge-triggered D Flip-Flop A positive-edge triggered D flip-flop QUESTION: What is the condition of this S-R flip- flop? QUESTION: What is the condition of this S-R flip- flop? Flip-Flops

29. SET  If there is a HIGH on the D input when a clock pulse is applied, the flip-flop will SET and the HIGH on the D input is stored by the flip-flop on the positive-going edge of the clock pulse (In the SET state, flip-flop is storing 1) RESET  If there is a LOW on the D input when a clock pulse is applied, the flip-flop will RESET and the LOW on the D input is stored by the flip-flop on the positive-going edge of the clock pulse (In the RESET state, flip-flop is storing 0) Edge-triggered D Flip-Flop (Function of +ve e-t) Flip-Flops

30. INPUTSOUTPUTS COMMENTS DCLKQQ 1  10 SET (stores a 1) 0  01 RESET (stores a 0)  = clock transition LOW to HIGH Edge-triggered D Flip-Flop (+ve e-t) Truth Table Flip-Flops

31.  Function of J-K Flip Flop is identical to that of the S-R flip flop in the SET, RESET and no-change conditions of operation  The difference is that the J-K flip-flop has no invalid states as does the S-R flip-flop  On each successive clock spike, the flip-flop changes to the opposite state. This mode is called toggle operation Edge-triggered J-K Flip-Flop Flip-Flops

32. Simplified logic diagram for a positive edge-triggered J-K flip flop Edge-triggered J-K Flip-Flop Flip-Flops

33. Truth Table for positive edge-triggered J-K flip-flop INPUTSOUTPUTS COMMENTS JKCLKQQ 00  Q0Q0 Q0Q0 No change 01  01RESET 10  10SET 11  Q0Q0 Q0Q0 Toggle (Opposite state) (Opposite state) = clock transition LOW to HIGH Q 0 = output level prior to clock transition Edge-triggered J-K Flip-Flop Flip-Flops

34. Flip-Flops Operating Characteristics  Define as the interval of time required after an input signal has been applied for the resulting output change to occur Propagation delay time t PLH Propagation delay t PLH as measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output

35. Propagation delay time t PHL Propagation delay t PHL as measured from the triggering edge of the clock pulse to the HIGH-to-LOW transition of the output Flip-Flops Operating Characteristics

36.  Define as the minimum interval required for the logic levels to be maintained constantly on the inputs (J and K, or S and R, or D) prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop Set-up time (t s ) Flip-Flops Operating Characteristics

37.  Define as the minimum interval required for the logic levels to remain on the inputs after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop Hold time (t h ) Flip-Flops Operating Characteristics

38. Maximum Clock Frequency (f max )  The highest rate at which a flip-flop can be reliably triggered.  At clock frequencies above the maximum, the flip-flop would be unable to respond quickly enough, and its operation would be impaired Power dissipation  P = V cc x I cc END Flip-Flops Operating Characteristics