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11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 20081 A New Data Acquisition System based on Asynchronous Technique Yu. Bocharov, A. Gumenyuk, A. Klyuev, A. Simakov
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11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 20082 To compare architectures Analog FIFO per channel vs. Dig.FIFO per ADC To estimate a data loss for systems based on architectures compared by a Monte Carlo modeling To define the ADC specifications Objectives
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11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 20083 A New Readout System Architecture A New Readout System Architecture As an example – 2 ADC per 128 AFE channels Other variants – 1, 4 ADC PD – peak detector Main Feature Digital FIFO per ADC against Analog FIFO per channel
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11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 20084 Step 1 When a hit occurs in a channel PD locks the this channel in and sends EVENT signal to the control unit
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11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 20085 Step 2 The control unit writes a channel number and a time stamp into a Dual-port Memory/FIFO. Any type of arbiter may be used to prevent conflicts of writing
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11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 20086 Step 3 The High Speed ADC converts the outputs of channels which numbers are stored in FIFO
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11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 20087 Step 4 Converted data conjunctly with a channel number and a time stamp are transmitted to the external memory bus
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11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 20088 Step 5 When the conversion is finished a control unit initializes PD and corresponding MEM content and connects ADC to the next channel or switches it to a shutdown state if FIFO is empty
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11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 20089 Structure of the arbitration logic for analog de-randomizer (2007) Structure of the arbitration logic for analog de-randomizer (2007)
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11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 200810 Simulation of the synthesized arbitration logic Simulation of the synthesized arbitration logic
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11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 200811 Arbitration logic Area Estimation (Encounter, Faraday standard cells, UMC 0.18) Arbitration logic Area Estimation (Encounter, Faraday standard cells, UMC 0.18)
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11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 200812 Total of hits per cycle probability (%) for 128 (a), 64 (b), 32 (c) channel system at 5% channel occupancy for Poisson process Mean – 6.4, 3.2, 1.6 a b c
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11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 200813 12 % MSPS CBM-XYTER data loss as a function of total ADC-channels throughput at the best (1) and worse (2) – numerical simulation
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11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 200814 λ – Poisson distribution parameter, M – number of channels per ADC, θ – channel occupancy, μ – max number of channels may be A-D converted within one cycle Analytical estimation of a data loss for a new readout system Analytical estimation of a data loss for a new readout system
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11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 200815 1 2 3 % MSPS Data loss of a new readout system as function of ADC throughput @ 32 (1), 64(2), 128(3) channels per ADC – analytical and numerical
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11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 200816 Figure of merit (FOM) commonly used for ADC characterization P d – power dissipation ENOB – effective number of bits f s – sampling frequency (ENOB spec)
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11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 200817 Summary CBM-XYTER 120 MSPS, 128 mW, FOM < 10.7 pJ - 1 AD/chip 60 MSPS, 64 mW, FOM < 10.7 pJ - 2 AD/chip 30 MSPS, 32 mW, FOM < 10.7 pJ - 4 AD/chip Advantage – reduced ADC requirements New architecture 160 MSPS, 128 mW, FOM < 8.0 pJ - 1 AD/chip 105 MSPS, 64 mW, FOM < 6.1 pJ - 2 AD/chip 75 MSPS, 32 mW, FOM < 4.3 pJ - 4 AD/chip Advantage – elimination of 512 analog MEM cells ADC specs @ Pd = 1 mW/channel and ENOB = 6.6 bit (100 quantization levels) Max data loss level = 0.01%
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