1. Lecture 2: Basic Instructions EEN 312: Processors: Hardware, Software, and Interfacing Department of Electrical and Computer Engineering Spring 2014, Dr. Rozier (UM)

2. COURSE PLAN FOR TODAY 1.Lab 1 Introduction 2.Introduction to debugging with GDB 3.Introduction to Instructions 4.Lab 1 GDB demo

3. LAB 1

4. Lab 1: Binary Bomb Quick change to the syllabus – Due dates will now be the Monday before the next lab goes out. Gives everyone an automatic extension for all labs. Lab 1 is out today Due Monday, February 3 rd at 11:59pm.

5. Lab 1: Binary Bomb Your task is to solve a series of six stages by finding the password. You will get a unique compiled binary. You will need to disassemble this binary to find the passwords.

6. Lab 1: Binary Bomb If you enter a wrong password, the bomb will “explode” and notify us. The bomb has tamper proof protections. Do not try to run it on a non-lab computer, or it will notify us and abort! Each explosion deducts half a point from your lab score.

7. Lab 1: Binary Bomb Assignment PartPoints Phase 110 Phase 210 Phase 310 Phase 410 Phase 515 Phase 615 Write up10 Explosions-0.5 each 80 pts maximum score

8. Lab 1: Binary Bomb If you do things right, your bomb should never blow up! Think carefully! Use the debugger gdb to step through and analyze the program. – Figure out what the code is doing to check for a correct result, and how to pass the checks.

9. Lab 1: Binary Bomb Start early! The lab will not be easy! Bomb download site: – http://een312.performalumni.org:15213/ http://een312.performalumni.org:15213/ Bomb scoreboard: – http://een312.performalumni.org:15213/scorebo ard http://een312.performalumni.org:15213/scorebo ard

10. GDB: THE GNU DEBUGGER

11. gdb: The GNU Debugger Standard and portable debugger for Unix and Unix-like systems. – Originally written in 1986 – Very active tool. Three software releases in 2013. – Still the gold-standard for debugging Enables users to trace, alter, and execute computer programs in a controlled environment.

12. gdb: The GNU Debugger Most useful features – Step through program execution, line by line, or instruction by instruction. – Examine the values of variables and registers. – Trap system signals. – Set breakpoints to halt execution at any point. – Watch variables to see when they change.

13. gdb: The GNU Debugger Some commands – run – executes the program – break - sets a breakpoint at label – break * - sets a breakpoint at the address – print - prints the register’s value – stepi – step through one assembly instruction

14. gdb: The GNU Debugger Some commands – disas - disassemble the code at label. – continue – continue execution after halting at a breakpoint. – info [break| ] - give information about breakpoints or registers – info r – display the value of all registers – x/ - display the value stored at in the format specified by

15. gdb: The GNU Debugger We will show an example towards the end of class of the debugger in action.

16. BASIC INSTRUCTIONS

17. Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets – But with many aspects in common Early computers had very simple instruction sets – Simplified implementation Many modern computers also have simple instruction sets

18. MIPS vs ARMv6 The book uses the MIPS instruction set. We will be using ARMv6 in our labs. Both are RISC (reduced instruction set computer) architectures. – Many similarities.

19. MIPS Used in many embedded systems – Routers, gateways – Playstation 2 and PSP Invented by Prof John Hennessy at Stanford, the first RISC architecture.

20. ARM Introduced in 1985 Focused on low-power friendly operation. Since 2005, over 98% of all mobile phones had at least one ARM processor. Over 37 billion ARM processors in use in 2013. Rapidly becoming the dominant processor architecture in the world.

21. Instructions C code: – f = (g + h) – (i + j); Compile ARM code: – add r0, r3, r4 # temp t0 = g + h – add r1, r5, r6 # temp t1 = i + j – sub r2, r0, r1 # f = t0 – t1

22. Register Operands Instructions use registers for operands. Registers are extremely fast SRAM locations that are directly accessible by the processor. – Very fast, but very expensive, so very small.

23. Registers Each register holds a word (4 bytes). Registers r0-r12 are general purpose. NameFunctionNameFunction r0General Purposer8General Purpose r1General Purposer9General Purpose r2General Purposer10General Purpose r3General Purposer11General Purpose r4General Purposer12General Purpose r5General Purposer13Stack Pointer r6General Purposer14Link Register r7General Purposer15Program Counter

24. Registers Registers r13 – r15 have special purposes The PC, r15, is very dangerous. NameFunctionNameFunction r0General Purposer8General Purpose r1General Purposer9General Purpose r2General Purposer10General Purpose r3General Purposer11General Purpose r4General Purposer12General Purpose r5General Purposer13Stack Pointer r6General Purposer14Link Register r7General Purposer15Program Counter

25. Registers The register r13 holds the stack pointer – Also called sp – Points to a special part of memory called the stack. – More about this later.

26. Registers The register r14 holds the link register – Also called lr – Holds the value of a return address that allows for fast and efficient implementation of subroutines.

27. Registers The register r15 holds the program counter – Also called pc – Holds an address of an instruction. Keeps track of where your program is in its execution of machine code. – PC holds the address of the instruction to be fetched next.

28. Registers One additional register, the “current program status register” Four most significant bits hold flags which indicate the presence or absence of certain conditions. 3130292827…87654…0 NZCVReservedIFTMODE

29. Registers N – negative flag Z – zero flag C – carry flag V – overflow flag 3130292827…87654…0 NZCVReservedIFTMODE

30. Registers N – set by an instruction if the result is negative (set equal to the two’s complement sign bit) N – negative flag Z – zero flag C – carry flag V – overflow flag 3130292827…87654…0 NZCVReservedIFTMODE

31. Registers Z – set by an instruction if the result of the instruction is zero. N – negative flag Z – zero flag C – carry flag V – overflow flag 3130292827…87654…0 NZCVReservedIFTMODE

32. Registers C – set by an instruction if the result of an unsigned operation overflows the 32-bit register. Can be used for 64-bit arithmetic N – negative flag Z – zero flag C – carry flag V – overflow flag 3130292827…87654…0 NZCVReservedIFTMODE

33. Registers V – works the same as the C flag, but for signed operations. N – negative flag Z – zero flag C – carry flag V – overflow flag 3130292827…87654…0 NZCVReservedIFTMODE

34. MORE ABOUT THESE LATER…

35. The Memory Hierarchy

36. Load-Store Architecture RISC architectures, like ARM and MIPS utilize a load-store architecture. Memory cannot be part of arithmetic operations. – Only registers can do this Access memory is through loads and stores.

37. Register Memory Architecture Featured on many CISC architectures, like x86 Allows direct access to memory by instructions.

38. Load Store and ARM Register space is pretty cramped!!! LoaD to a Register with LDR SToRe to memory with STR ldr, [ {, }] – Loads a byte from + into str, [ {, }] – Stores a byte from into +

39. Load Store and ARM Example – ldr r0, [r1,r2] Load data from location r1+r2 into r0. – ldr r0, =string Load data from label string into r0. Special cases exist, see ARM manual – Example: ldrb loads a single byte, padded with zeros.

40. Constants or Immediates Operands can contain registers, or immediate values. – An immediate is like a constant – Represent immediates as follows: #20 add r0, r1, #20 – adds 20 to the value of r1 and stores it in r0.

41. Arithmetic Instructions Addition – add, adc, adds, etc Subtraction – sub, sbc, rsb, subs, etc Multiply – mul, mla, etc

42. Move Instruction mov, – mov r0, r1 – copy the contents of r1 into r0. – mov r0, #20 – copy an immediate value of 20 into r0. mvn, – Move negative, negates operand before copying it.

43. Compare Instructions cmp, cmn, Don’t change the operands, update special status register flags. cmp – subtracts operand2 from operand1 and discards the result. cmn – adds operand2 to operand1 and discards the result.

44. Status Register Flags Compare instructions and the special “S” versions of instructions (adds, subs, movs) set the status register flags. Can be used with conditional suffixes to make conditionally executed instructions.

45. Conditional Execution Just as the special “S” suffix can be added to set status flags, other suffixes can be added to act on status flags.

46. EQ: Equal Z=1 Using the EQ suffix on an instruction will cause it to only be executed if the zero flag is set. cmp r0, r1 @ Set flags based on r0-r1 adds r0, r1, r2 @ Set flags based on r0 = r1 + r2 movs r0, r1 @ Set flags based on r0 = r1

47. EQ: Equal Z=1 Using the EQ suffix on an instruction will cause it to only be executed if the zero flag is set. Example cmp r0, r1 @ Set flags based on r0-r1 addeq r2, r0, r1 @ Conditional addition

48. NE: Equal Z=0 Using the NE suffix on an instruction will cause it to only be executed if the zero flag is not set.

49. Other conditional suffixes VS – overflow set, V=1 VC – overflow clear, V=0 MI – minus set, N=1 PL – minus clear, N=0 CS – carry set, C=1 CC – carry clear, C=0 AL – always, unconditional NV – never, unconditional

50. Multiple Conditional Suffixes HI – higher (unsigned), C=1 and Z=0 – Unsigned greater than LS – lower (unsigned), C=0 and Z=1 – Unsigned less than GE – greater or equal (signed), N=1, V=1 OR N=0, V=0 – Signed greater than or equal to LT – less than (signed), N=1, V=0, OR N=0,V=1 – Signed less than

51. Multiple Conditional Suffixes GT – greater than (signed), N=1, V=1, OR N=0, V=0 AND Z=0 – Signed greater than LE – less than or equal (signed), N=1, V=0, OR N=0, V=1, OR Z=1 – Signed less than or equal to

52. LAB 1 GDB DEMO

53. WRAP UP

54. For next time Read Chapter 2, Sections 2.6 – 2.8 Learn about control, branch, loops, etc.