2. Partition-Driven Standard Cell Thermal Placement Guoqiang Chen Synopsys Inc. Sachin Sapatnekar Univ of Minnesota For ISPD 2003

3. Outline zIntroduction zThermal Placement ySimplified Thermal Model for Partitioning yPartition-Driven Thermal Placement zExperimental Results zConclusion

4. zThermal problem is projected to be a major bottleneck for the next- generation circuits zPlacement is the natural starting point in the design process where we take thermal problem into consideration Why Thermal Placement? Courtesy Intel

5. Typical Heat Conduction Environment of the Wafer x z y heat sources... ambient temperature... wafer... + ~ + ~

6. Thermal Equation zPartial differential equation yWe will consider the steady state version: Poison Equation zApplying finite difference method and eliminating internal mesh nodes yields G T = P yG is the thermal conductance matrix yT and P are the temperature and power density vector over mesh nodes on the top surface of the wafer

7. Thermal Placement zMinimize max. temperature variation zProblem formulation: Find permutation  of P i : {1, …,n}  {1,…n} such that δT = max|T i -T i,neighbor | is minimized (No wire-length/timing considerations) zThis is a NP-hard problem already zPrevious work yChu and Wong, TCAD98: matrix synthesis yTsai and Kang, TCAD00: simulated annealing based

8. Partition-Driven Thermal Placement zPartition based placement methods are powerful methods to solve the placement problems zCould we easily extend Tsai and Kang’s work for partition driven placement?

9. Two Obvious Approaches z Use equation G T=P directly at each partitioning step y During the early partitioning stages, we do not know where the cells will be eventually located y Too expensive to compute z Compute the desired power distribution, and try to match the power distribution during partition stages y Difficult to get an exact budget for the power distribution y We are not optimizing the temperature directly

10. Outline zIntroduction zThermal Placement ySimplified Thermal Model for Partitioning yPartition-Driven Thermal Placement zExperimental Results zConclusion

11. Simplified Thermal Model for Partitioning zIt is known that Poisson equation can be solved with Multigrid method effectively zOur model is motivated by one interpretation of the mutligrid methods

12. Multigrid Solver for Poisson Equation zThe multi-grid method solves different spatial frequency components at different levels of mesh. yLow-frequency components: coarse mesh yHigh-frequency components: fine mesh zThe temperature distribution across the chip can be considered as a superposition of low spatial frequency components and high spatial frequency components

13. Top-down Partition Process Thermal grids Standard cell This process can be considered as series of operations on a gradually refined meshes

14. Basic Ideas zAt each partition level, we are only concerned about the spatial distribution of the temperature corresponding to the current coarse grids zIn the early stage of partitioning, we are mainly concerned about the low frequency components zAs the mesh is refined, higher frequency terms, corresponding to local variation of temperature, will be considered

15. At each partition level, we are only interested in controlling the temperature differences between the current coarse grids. Simplified Thermal Model We will assume that the temperature within each grid is same.

16. The First Step in Top-down Partitioning z Original Equation:GT=P T, P are N 2 x 1 vector, and G is a N 2 x N 2 matrix 1 N 1 N TLTL TRTR zNow the equation is simplified to:

17. zThis process can be extended to general case where we partition the chip into k regions zResulting G matrix is a k x k matrix and it is positive definite Extension to General Case

18. Outline zIntroduction zThermal Placement ySimplified Thermal Model for Partitioning yPartition-Driven Thermal Placement zExperimental Results zConclusion

19. Before Partitioning a New Level Compute the simplified thermal conductivity matrix G Prepare the matrix for incremental update

20. Before Partitioning of a Block zGenerate multiple initial solutions and compute δT zSet the thermal budget for the current partition to be (1-α) δT min + α δT max z Pick the initial partition with lowest δT as the initial solution for partitioner

21. When We Move One Cell zCompute power changes induced by the cell movement zCompute temperature changes for blocks that are affected by the move. zCompute δT for the current move, and check against the budget to see if we will accept the move or not

22. Outline zIntroduction zThermal Placement ySimplified Thermal Model for Partitioning yPartition-Driven Thermal Placement zExperimental Results zConclusion

23. Experimental Results

24. Maximum On-Chip Temperature Variation

25. Maximum Temperature

26. Conclusion zWe presented an simplified thermal model to take temperature directly as partition constraints. zThe basic idea is we want to control different spatial frequency of the temperature variation at different partition level zWe proposed a top-down partition-driven placement scheme to use the simplified model

27. End Thank You