1. Project 1: DRAM timing violation due to PV Due to PV, transistor and capacitor may have variations in their dimensions, causing charging time of a cell to vary Situation is becoming worse with smaller technologies Threatens yield

2. Initial Study

3. Challenges: Maintain yield – How to overcome slow-to-write cells? Naïve Solution: there are both fast and slow cells. Can fast cells balance slow cells? Distribution Data

4. Issues Cannot do it at cell granularity. The memory controller would not be able to handle different write speed at cell level A practical way is to handle it at the row level The write speed of a row is determined by its slowest cell: is it good enough, or do we need a different granularity, say a chunk (sub-row, super- row)? Cost of fine granularity: the memory controller needs to bookkeep the information – a huge hardware overhead

5. Issues continued Problem of coarse granularity: limited by the slowest cell. May not be able to exploit the fast cells Question 1: what is the best granularity that the memory controller should consider in distinguishing different write speeds?

6. Another Question Suggestions: use only a few write times, and put memory chunks into bins Question 2: given a chunk size, how to decide  ?

7. A Reference Reading Bo Zhao et al. “Variation-Tolerant Non- Uniform 3D Cache Management in Die Stacked Multicore Processor”, in MICRO 2009.

8. Tools You May Need DRAMSim: – Paul Rosenfeld, Elliott Cooper-Balis, and Bruce Jacob. Dramsim2: A cycle accurate memory system simulator. IEEE Comput. Archit. Lett., 10(1):16–19, January 2011. VARIUS: – S. Sarangi, B. Greskamp, R. Teodorescu, J. Nakano, A. Tiwari, and J. Torrellas. Varius: A model of process variation and resulting timing errors for microarchitects. IEEE Transactions on Semiconductor Manufacturing, 21(1):3–13, 2008

9. WoM Encoding for PCM Slow write operation − Write blocks read, causes slowdown − SET: long latency (~8x of read) − RESET: short latency (~ same to read) time Power RESET SET

10. 11111111 PCM Memory PreSET Scheme [Qureshi_hpca’13] Exploit asymmetry (slow SET vs. fast RESET) in write operations Perform SET ahead of actual write proactive-SET − Proactively SETs (proactive-SET) dirty cache line; write- back write − Only RESETs are performed when actually written (write- back write) to memory (fast write). 10 DRAM$ Proactive SET Eviction to 01010101 10101010 01010101 11111111 ✗ slow ✓ fast 11111111

11. PreSET Increases no. of Bit Changes 11 For 128B line, − Baseline sets 91 bits and reset 77 bits; − PreSET sets 180 and resets 200. 2.6X 1.98X

12. PreSET Overall Effects Positive: − Improves performance by 34% − Decreases Energy-Delay-Product (EDP) by 24% Drawbacks: − Greatly increases write power (225%) & system power (30%); − Impairs lifetime of PCM, ~60%. 12 Can we cut down PreSET’s power consumption without losing performance?

13. 10111011 011 1 101 11 111 Write-Once Memory (WoM) First introduced for uni-direction write-once memories: 0  1 [Rivest & Shamir’82] Recently adopted in Flash [Jiang A.’07] – Cut the no. of erasures by half – Improved write performance and lifetime 13 000 001 010 100 111 110 101 00 01 10 11 2-bit data1 st -write2 nd -write 00 111000 01 110001 10 101010 11 011100 WoM code for PCM Both writes have RESETs only Original WoM code

14. WoM-SET A proactive-SET based write scheme using WoM code. 14 01 01 110 001 110 110 11 11 111 111 10 01 01 00 101 110 110 111 10 00 01 00 101 000 110 111 11 11 BaselinePreSETWoM-SET Memory Line time 3RESET, 1SET 11RESET, 9SET 5RESET, 5SET

15. Questions to Solve What if we just apply WoM codes to the baseline (i.e. without PreSET)? How would that improve (or degrade) the baseline? After applying code 1 and code 2, how to proceed on the third write of a cell? – Option 1, write code 1 directly – Option 2, use PreSET and code 1 Which one is better?