1. CSCE 2214 Lab 01 Week 01 Sen Ma

2. Information Lab Time : Mon, Wed : 4:10pm – 5:55pm Fir : 2:00 – 3:45 Office Hours: Mon, Wed : 3:00pm – 4:00pm Fir : 1:00 – 2:00 Room : JBHT 240 Email : senma@uark.edu

3. Tired of taking Notes? Try QR Code 1/10/13

4. Pre-Knowledge Digital Design VHDL Hans on Lab How to Be Patient!!

5. Syllabus for Labs 1- Pre lab (30 point) must be printed and turned in at the beginning of lab. 2- Lab report (70 point) must be printed and turned in at the beginning of lab. If you could not complete the lab in the given lab time, you should try to finish it in your spare time later.

6. Important Links http://csce.uark.edu/~senma https://moodle.csce.uark.edu/ 1/10/13

7. Need yourself enrollment with the correct key. The enrollment keys are L001 Mon : Lab2214@1 Setup moodle Where you check grades

8. Need yourself enrollment with the correct key. The enrollment keys are L002 Wed : Lab2214@2 Setup moodle Where you check grades

9. Need yourself enrollment with the correct key. The enrollment keys are L003 Fri : Lab2214@3 Setup moodle Where you check grades

10. Format for the HW & Lab Report http://csce.uark.edu/~senma/CSCE2214/schedule.html Download Homework Cover Page Download Report Cover Page Using QR Code Gen to generate your QR code. Download Format Always use Cover Page with your HW, Lab Report or Pre-labs.

11. Format for the HW & Lab Report http://csce.uark.edu/~senma/CSCE2214/schedule.html Download Homework Cover Page Download Report Cover Page Using QR Code Gen to generate your QR code. Download Format http://csce.uark.edu/~senma/CSCE2214/Slides/Index.p df Always use Cover Page with your HW, Lab Report or Pre-labs.

12. Tools Xilinx ISE C:\ProgramData\Microsoft\Windows\Start Menu\Programs\Xilinx ISE Design Suite 14.7\ISE Design Tools\64-bit Project Navigator License Problem: LM_LICENSE_FILE 1717@comp.uark.edu XILINXD_LICENSE_FILE 2011@hthreads.ddns.uark.edu

13. Demo 1/10/13

14. Hands on Lab Counter_10 Clk En Rst Fout Cout 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

15. Entity entity Counter_10 is port( CLK:instd_logic; En:instd_logic; Rst:instd_logic; Cout:outstd_logic; Fout:outstd_logic_vector(3 downto 0)); end Counter_10; 1/10/13

16. architecture architecture Behavioral of Counter_10 is signaltime:std_logic_vector(3 downto 0); begin TT:process(CLK,Rst,En) Begin if (CLK='1' and CLK'event) then if (Rst = '1') then time <= "0000"; else if (En = '1') then if (time < "1001") then time <= time+1; if (time = "1000") then Cout <= '1'; else Cout <= '0'; End if; else time <= "0000"; Cout <= '0'; End if; End process; Fout <= time; end Behavioral; 1/10/13

17. The Lab for next week Option 1 : Clock Create a counter_60 Create a counter_24 Using TWO counter_60 and ONE counter_24 to Create a Clock

18. The Lab for next week Option 1 : Clock Create a counter_60 Create a counter_24 Using TWO counter_60 and ONE counter_24 to Create a Clock