2. Scoreboarding Simulation Advanced Computer Architecture Linda Wills Animation by: Chris Lee

3. What is Scoreboarding? Scoreboarding is a technique used to prevent data and structural hazards. It does this by keeping relevant information stored in a data structure comprising of an instruction queue, a table of function unit status, and a table for register result status.

4. Properties of Scoreboarding  Large data structure to hold relevant information  In-order issue, but out-of-order completion  Can issue an instruction when:  All earlier instructions have been issued  The needed functional unit is free  No other active instruction has the same destination register (WAW)

5. Properties of Scoreboarding (Cont)  Reads operands when both become available  Executes the instruction when the instruction has been issued and both operands have been read  Writes result to destination register (Rd) after all pending instructions that have Rd as a source operand have read their operands (WAR).

6. A Closer Look at Scoreboarding Tables  Three types of tables: Instruction Queue Status Keeps track of instructions and their progress. Function Unit Status Keeps track of what hardware is currently in use and what it will need to read from and write to. Register Result Status Tracks which functional unit is computing a register's value.

7. Instruction Queue Status Instruction (Operation, Resultant, Operand1, Operand2) Issued - has the instruction been issued? Op. Read - are both operands available and have they been read? Ex. Cmpl. - Has the execution of this instruction completed yet? Result - Has the result of this instruction been written back to the register?

8. Function Unit Status List of functional units Busy - Is this functional unit currently executing? Op - Operation is this functional unit performing Dest - Name of destination register Sop1, Sop2 - Source operand 1 and 2 respectively Unit1, Unit 2 - Functional unit currently computing operand 1 and 2 respectively

9. Register Result Status Keeps a list of all registers Keeps a record of which functional unit is computing the value of this register.

10. An Example We have the following program: LFF6,34(R2) LFF2,45(R3) MULTFF0,F2,F4 SUBFF8,F6,F2 DIVF F10,F0,F6 ADDFF6,F8,F2 Assume the initial state is that the first instruction has completed. The Second LF has just completed execution and is about to write its results.

11. An Example (Cont) Suppose we have the following hardware: 1 ALU for integer operations (including loads and stores), called 1[i], with a latency of 1 cycle. 2 FP multiplication units, 2[*1] and 3[*2], with latencies of 10 cycles each. 1 FP addition and subtraction unit, 4[+], with a latency of 2 cycles 1 FP division unit, 5[/], with a latency of 40 cycles 1[i] 2[*1]3[*2] 4[+]5[/] 1 Cycle 10 Cycles 2 Cycles40 Cycles

12. 2. Function Unit Status FUBusyOpDestSop1Sop2Unit1Unit2Rdy1Rdy2 1[i]YLoadF2R3 * 2[*1]N 3[*2]N 4[+]N 5[/]N Which instructions can issue? Let’s issue as many as is allowed and fill in the status tables.

13. 2. Function Unit Status FUBusyOpDestSop1Sop2Unit1Unit2Rdy1Rdy2 1[i]YLoadF2R3 * 2[*1]YMultF0F2F41[i]NoYes 3[*2]N 4[+]N 5[/]N In this step, the MULTF was issued. The changes are noted in Red.

14. 2. Function Unit Status FUBusyOpDestSop1Sop2Unit1Unit2Rdy1Rdy2 1[i]YLoadF2R3 * 2[*1]YMultF0F2F41[i]NoYes 3[*2]N 4[+]YSubF8F6F21[i]YesNo 5[/]N In this step, the SUBF was issued. The changes are noted in Red.

15. 2. Function Unit Status FUBusyOpDestSop1Sop2Unit1Unit2Rdy1Rdy2 1[i]YLoadF2R3 * 2[*1]YMultF0F2F41[i]NoYes 3[*2]N 4[+]YSubF8F6F21[i]YesNo 5[/]YDivF10F0F62[*1]NoYes In this step, the DIVF was issued. The changes are noted in Red.

16. 2. Function Unit Status FUBusyOpDestSop1Sop2Unit1Unit2Rdy1Rdy2 1[i]YLoadF2R3 * 2[*1]YMultF0F2F41[i]NoYes 3[*2]N 4[+]YSubF8F6F21[i]YesNo 5[/]YDivF10F0F62[*1]NoYes In this step, the ADDF was attempted but not issued. Why was this not issued? Answer Because there is no free floating point adding unit, this instruction cannot be issued at this time.

17. 2. Function Unit Status FUBusyOpDestSop1Sop2Unit1Unit2Rdy1Rdy2 1[i]N 2[*1]YMultF0F2F4Yes 3[*2]N 4[+]YSubF8F6F2Yes 5[/]YDivF10F0F62[*1]NoYes The Second LF Writes Back The changes are noted in Red.

18. 2. Function Unit Status FUBusyOpDestSop1Sop2Unit1Unit2Rdy1Rdy2 1[i]N 2[*1]YMultF0F2F4 * * 3[*2]N 4[+]YSubF8F6F2 * * 5[/]YDivF10F0F62[*1]NoYes The MULTF and SUBF can now read needed operands. The changes are noted in Red.

19. 2. Function Unit Status FUBusyOpDestSop1Sop2Unit1Unit2Rdy1Rdy2 1[i]N 2[*1]YMultF0F2F4 3[*2]N 4[+]YSubF8F6F2 5[/]YDivF10F0F62[*1]NoYes The SUBF instruction will complete before the MULTF. The changes are noted in Red. * * * *

20. 2. Function Unit Status FUBusyOpDestSop1Sop2Unit1Unit2Rdy1Rdy2 1[i]N 2[*1]YMultF0F2F4NoYes 3[*2]N 4[+]YAddF6F8F2 5[/]YDivF10F0F62[*1]NoYes The SUBF Writes Results and Frees up FU4, Allowing I4 to be Issued. The changes are noted in Red. Question Which instruction should finish next? * *