1. Performance Characterization and Architecture Exploration of PicoRadio Data Link Layer Mei Xu and Rahul Shah EE249 Project Fall 2001 Mentor: Roberto Passerone

2. Project Description Complete the data link layer functional description in VCC (initialization & maintenance blocks) Develop target architecture platforms for implementation Use VCC Architectural Services to estimate performance on different architectures Identify an architecture that is suitable for the implementation of PicoNode III

3. Motivation Identify missed events Estimate system-level performance Provide data on the usage of processors, buses, and other shared devices Provide idea of potential target architectures and their characteristics

4. Data Link Layer – Major Blocks Initialization & Maintenance Block Local Address Manager Neighbor Search Block Control Message Packetization Block Control Message Dispatcher Transmit Data Path Receive Data Path Transmit/Receive Controller Medium Access Control (MAC) Control Data

5. Data Link Layer Behavior

6. Basic Y-Chart BehaviorArchitecture Mapping Flow to implementation Describe & verify behavior Describe architectures Explore HW/SW design tradeoffs Integrated flow to implementation

7. The VCC Design Flow

8. Target Architectures Architecture 0 – ASIC only Architecture 1 – CPU only Architecture 2 – ASIC and CPU (hybrid)

9. Architecture 1: ARM CPU Only

10. Architecture Memory  ARM 7 Core  eCos RTOS – Round Robin  Time Sliced Bus  Simple Memory

11. CPU Utilization vs. Clock Speed Loss of events

12. CPU Latency vs. Clock Speed

13. CPU Utilization at 100khz

14. Architecture 2: ARM CPU + ASIC

15. Architecture Memory  ARM 7 Core  eCos RTOS – Round Robin  ASIC  Time Sliced Bus  Simple Memory

16. Mapping

17. Mapping of Major Blocks Initialization & Maintenance Block Local Address Manager Neighbor Search Block Control Message Packetization Block Control Message Dispatcher Transmit Data Path Receive Data Path Transmit/Receive Controller Medium Access Control (MAC) ASIC ARM

18. CPU Utilization vs. Clock Speed Loss of events

19. CPU Latency vs. Clock Speed

20. CPU Utilization at 10kHz

21. RTOS Gantt Chart (5kHz) Tx and Rx block take large time

22. Some Observations Very bursty system since nodes are mostly sleeping  High peak to average load  Low resource utilization  Power down of resources necessary Control Path better suited to hardware Data Path better suited to software

23. Conclusions Hybrid Architecture vs. only CPU: Lower clock speed needed Will result in lower power consumption Hybrid Architecture vs. only ASIC: Higher latency More flexibility

24. Possible Improvements to VCC Native support for power performance estimation Interface with network simulators to simulate large networks Runtime linking Trace driven simulations Better characterization of architectural resources

25. Future Work Do a power performance estimation Simulate the whole node – application, network & data link layer Design power manager and estimate node performance