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The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – Lab 7 MOSFET Parameters and Scaling Effects Jason Woytowich Ritu Bajpai November 2, 2006
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CMOS Scaling Devices are constantly shrinking in an effort to increase the number of devices on a chip. The state-of-the-art mass production is moving into ~65nm. Clock speeds are scaled up to increase performance.
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Effects on the Device Short-channel effects on VT Velocity saturation Gate leakage current (IG) Subthreshold current (ID)
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Effects on the Circuit Increased power consumption. Leads to decreased supply voltage and smaller noise margins. Increased role of wiring resistance, inductance and capacitance. Interconnect coupling IR Drop Electromigration
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Spice MODELS The standard spice model is not sufficient to capture all of these effects. There have been many upgrades to it in order to increase it’s effectiveness. Level 1~5 Parameters Level 49~100 Parameters
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Review of Spice Parameters.model nmos nmos Level=1 + Vto=1.0Kp=3.0E-5Gamma=0.35 + Phi=0.65Lambda=0.02Tox=0.1u + Nsub=1.0E+15Nss=1.0E+10Ld=0.01u + Tpg=1.00Uo=700.0Af=1.2 + Kf=1.0E-26Is=1.0E-15Js=1.0E-8 + Pb=0.75Cj=2.0E-4Mj=0.5 + Cjsw=1.00E-9Mjsw=0.33Fc=0.5 + Cgbo=2.0E-10Cgdo=4.00E-11Cgso=4.00E-11 + Rd=10.0Rs=10.0Rsh=30.0
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The “REAL” Data http://www.mosis.org/cgi- bin/cgiwrap/umosis/swp/params/ibm- 018/t67j_7wl_5lm_ma-params.txt file will serve as the real datahttp://www.mosis.org/cgi- bin/cgiwrap/umosis/swp/params/ibm- 018/t67j_7wl_5lm_ma-params.txt Save the above file as.md file. Make changes so as to correspond to the tanner.md format.
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The test setup
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The simulation A DC sweep of 100 points of VDS from 0 to 1.8V A Secondary sweep of 10 points of VGS from 0 to 1.8V.dc source VDS lin 100 0 1.8 sweep source VGS lin 10 0 1.8.include "C:\Documents and Settings\Student\Desktop\ECE122_Lab7\ml1_typ.md“ *replace with your path name *.include "C:\Documents and Settings\Student\Desktop\ECE122_Lab7\IBM_018u.md“// put your pathname.print dc i(M1,D) * Main circuit: MosfetTest M1 D G Gnd Gnd NMOS L=180n W=1u AD=66p PD=24u AS=66p PS=24u VGS G Gnd 5.0 VDS D Gnd 5.0 * End of main circuit: MosfetTest
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