1. 1

2. 2 Instructions: Words of the language understood by CPU Instruction set: CPU’s vocabulary Instruction Set Architecture (ISA): CPU’s vocabulary together with parts of machine and their function that must be mastered by a user to produce correct, compact, and fast program.

3. 3 Figure 5.1 Memory and processing subsystems for MiniMIPS. 5.1 Abstract View of Hardware

4. 4 Figure 5.2 Registers and data sizes in MiniMIPS.

5. 5 Figure 5.3 A typical instruction for MiniMIPS and steps in its execution. 5.2 Instruction Formats

6. 6 Figure 5.4 MiniMIPS instructions come in only three formats: register (R), immediate (I), and jump (J).

7. 7 Figure 5.5 The arithmetic instructions add and sub have a format that is common to all two-operand ALU instructions. For these, the fn field specifies the arithmetic/logic operation to be performed. add: 32 sub: 34 and: 36 or: 37 and: 38 or: 39 5.3 Simple Arithmetic and Logic Instruction

8. 8 Figure 5.6 Instructions such as addi allow us to perform an arithmetic or logic operation for which one operand is a small constant. In the case of that one operand of an arithmetic or logical operation is a constant. addi: 8 andi: 12 ori: 13 xori: 14 Constant: -32768 to 32767

9. 9 Figure 5.7 MiniMIPS lw and sw instructions and their memory addressing convention that allows for simple access to array elements via a base address and an offset (offset = 4i leads us to the ith word). 5.4 Load and Store Inst Instructions lw: 35 sw: 43

10. 10 Figure 5.8 The lui instruction allows us to load an arbitrary 16-bit value into the upper half of a register while setting its lower half to 0s. Load upper immediate lui: 15 Application: to make a 32-bit constant.

11. 11 Figure 5.9 The jump instruction j of MiniMIPS is a J -type instruction which is shown along with how its effective target address is obtained.The jump register (jr) instruction is R-type, with its specified register often being $ra. 5.5 Jump and Branch Instructions j: 2 jr: 8 (go to loc whose address is in $ra) 4 high-order bits from PC (pseudodirect addressing)

12. 12 Branch less than zero Set less than Memory address: Multiplied by 4 + PC slt $s1, $s2, $s3# if ($s2)<($s3), set $s1 to 1, else to 0. slti $s1, $s2, 61# if ($s2)<61, set $s1 to 1, else to 0.

13. 13 5.6 Address Modes Addressing mode is the method by which the location of an operand is specified within an instruction e.g. ja1 in section 6.1 e.g. addi, andi, ori, xori e.g. lw, sw e.g. add, and, or, xor, nor e.g. j

14. 14 Implied addressing: operand comes from, or result goes to, a predefined place that is not explicitly specified in the instruction. E.g., ja1 (in section 6.1) Immediate addressing: operand if given in the instruction itself. E.g., addi, andi, ori, xori. Register addressing: operand is taken from, or result placed in, a specified register. Base addressing: operand is in memory and its location is computed by adding an offset (16-bit signed integer) to the contents of a specified base register. E.g., lw, sw. PC-relative addressing: same as base addressing, but with the register always being the program counter and the offset appended with two 0s at the right end. Pseudodirect addressing: the operand address is supplied as part of instruction, e.g., j

15. 15 Table 5.1 The 20 MiniMIPS instructions covered in Chapter 5.