1. SLHC SG: ATLAS Pixel G. Darbo - INFN / Genova SLHC SG, July 2004 ATLAS Pixel at SLHC G. Darbo - INFN / Genova Talk overview: A table with different High Luminosity scenarios for LHC is presented. The table is interpreted for the ATLAS Pixel Detector with some comments on the critical issues.

2. SLHC SG: ATLAS Pixel G. Darbo - INFN / Genova SLHC SG, July 2004 2 Stefan Scoreboard Table  Present ATLAS Pixel detector limits at high luminosity LHC  As today, we think that all options, but super bunch, can be taken in consideration for a partially redesigned Pixel Detector

3. SLHC SG: ATLAS Pixel G. Darbo - INFN / Genova SLHC SG, July 2004 3 Comments to SLHC for Pixel  Depending from the SLHC scenario some upgrade or redesign of the Pixel detector must be done. Today Pixel detector has some contingency to operate at higher integrated luminosity or event rate, but B-layer is the one which will impact first the limit of the technology.  Critical aspect for the Pixel detector @ SLHC are:  Sensor depletion voltage w.r.t. integrated dose. Oxygenated sensor have demonstrated to work up to 60 Mrad (3 yr @ B-layer, 10 yr @ layer1). New sensor design and R&D  ROSE, RD-50.  FE and MCC electronic chips. Some 0.25 µm ATLAS Pixel chips irradiated (by dosimetery error) to 100 Mrad with acceptable performance. Smaller geometry and thin gate oxides looks very rad- hard. Single Event Upset (SEU) is critical, and will get worse with smaller geometry. Opto-chip may need a placement at outer radii.  R/O. Luminosity increase has its impact in two ways: buffer overflows and saturation of links. MCC in addition is sensitive to trigger rate receiving only data passing LEV1. Layer1 & 2 use only 1/2 of the MCC design bandwidth  a second link can be added: replace of optoboard and adding a second fibre. B-layer needs a rethink of the chip architecture if SLHC push luminosity to its limits. 25 ns bunces are preferred, but 75 ns bunches can work  simulation. Superbunch seems far from any tracker design reach.

4. SLHC SG: ATLAS Pixel G. Darbo - INFN / Genova SLHC SG, July 2004 4 FE & MCC Rad-hard Issues  Present FE & MCC chips have some contingency in the rad-hard value expected for nominal LHC luminosity.  For an upgrade of the detector 0.13 µm CMOS technology seems a promising candidate:  First measurements for 0.13 µm shows that thin oxide gate devices has very low or no VT shift (see plot: Dual Gate have 5 nm oxide, other devices 2.2 nm or lower)  SEU is an other issue:  FE & MCC have replica logics to increase SEU tolerance;  0.13 µm has higher SEU X-section due to smaller geometry and lower VDD. Ref.: K. Einsweiler, On-detector Electronics for ATLAS ID Upgrade, US ATLAS Upgrade WS http://atlaspc3.physics.smu.edu/atlas/  0.13 µm chips can be developed in the time scale for SLHC (2012)

5. SLHC SG: ATLAS Pixel G. Darbo - INFN / Genova SLHC SG, July 2004 5 Inefficiencies @ High Luminosity B-Layer  Pixel telescope used at high intensity test beam to test inefficiencies induced by particle rates.  Plot show the missing hits (mainly due to FE chip R/O) Ref.: B.Osculati & L.Rossi, Pixel Week Feb’04 http://www.ge.infn.it/ATLAS/PixelWeek/Presentations/04-02-18_LR_HV_pixel_cables/04-02-18_LR_HV_pixel_cables.pdf

6. SLHC SG: ATLAS Pixel G. Darbo - INFN / Genova SLHC SG, July 2004 6 MCC & ROD R/O Inefficiencies MCC R/O architecture simulated for the FDR (24 event pileup + 100 kHz trigger rate) shows a good margin even for the B- layer at 80 Mb/sec data link (it is foreseen to use 160 Mb/sec) At high luminosity may be necessary to increase the number of RODs Simulation needed for different SLHC scenarios. Ref.: C. Schiavi, MCC FDR, Dec’02 http://www.ge.infn.it/ATLAS/ATLAS/Electronics/MCC-DSM/MCC-FDR/05.CS_Performance.pdf

7. SLHC SG: ATLAS Pixel G. Darbo - INFN / Genova SLHC SG, July 2004 7 Conclusion  Pixel Detector is one of the best candidate for tracking at SLHC in the region below 20 cm. But significant R&D is needed.  First upgrade at the horizon is the relatively limited B-layer (2010), this could already benefit from R&D in the sensor and electronic area (0.13 µm chips). It would be natural to use this upgrade as an intermediate test bench towards the “beyond the state of the art” of LHC.  In case all the R&D efforts are not enough to have a detector surviving the harsh SLHC environment at 5 cm from beam, we may still have the contingency to increase the radius of the Pixel detector, even if it is not what we prefer…