1. SG6 : FIT1001 Computer Systems S1 2006 1 Important Notice for Lecturers This file is provided as an example only Lecturers are expected to modify / enhance slides to suit their teaching style Lecturers are expected to cover the topics presented in these slides Lecturers can export slides to another format if it suits their teaching style (but must cover the topics indicated in the slides) This file should not be used AS PROVIDED – you should modify it to suit your own needs! This slide should be deleted from this presentation Provided by the FIT1001 SIG

2. www.monash.edu.au FIT1001- Computer Systems

3. www.monash.edu.au FIT1001- Computer Systems Lecture 6 Computer Program Execution Concepts

4. SG6 : FIT1001 Computer Systems S1 2006 4 Review – Last Week (remove for lect 2 or 3) This slide can be removed if you have 3 1 hour lectures from lecture 2 and 3 in the same week…..or just lecture 2 if you have a 2/1 split.

5. SG6 : FIT1001 Computer Systems S1 2006 5 Learning Objectives Understand the concepts of program execution and control the flow of a program Understand the basic concepts of the stack Understand the basic concepts of both hardware and software interrupts Describe how interrupts alter the normal flow of program execution in a computer system Define interrupt vectors and develop interrupt handlers Compare the characteristics of RISC machines versus CISC machines

6. SG6 : FIT1001 Computer Systems S1 2006 6 Content Name Program Execution Concepts Program Control Instructions Stacks Interrupts Case Studies of Real Architectures

7. www.monash.edu.au FIT1001- Computer Systems LECTURE 6 Program Execution Concepts

8. SG6 : FIT1001 Computer Systems S1 2006 8 Tutorial (remove if 1 st or 2 nd lecture) Should only be present in last lecture for the given week……unless you want otherwise!

9. SG6 : FIT1001 Computer Systems S1 2006 9 Instruction Processing The fetch-decode-execute cycle is the series of steps that a computer carries out when it runs a program. We first have to fetch an instruction from memory, and place it into the IR. Once in the IR, it is decoded to determine what needs to be done next. If a memory value (operand) is involved in the operation, it is retrieved and placed into the MBR. With everything in place, the instruction is executed. The next slide shows a flowchart of this process.

10. SG6 : FIT1001 Computer Systems S1 2006 10 Instruction Processing

11. www.monash.edu.au FIT1001- Computer Systems LECTURE 6 Program Control Instructions

12. SG6 : FIT1001 Computer Systems S1 2006 12 Transfer of Control Unconditional branch –e.g. branch to instruction at location xxxx Conditional Branch –e.g. branch to instruction at location xxxx if result of last operation was zero Skip –e.g. increment and skip next instruction if result is zero ISZ Register1  increment & skip if zero Branch xxxx  skip this if result was zero ADD A Procedure (subroutine) call

13. SG6 : FIT1001 Computer Systems S1 2006 13 Branch Instruction

14. SG6 : FIT1001 Computer Systems S1 2006 14 Nested Procedure Calls start address of Proc1 start address of Proc2 how does machine know where to go back to? STACK!

15. www.monash.edu.au FIT1001- Computer Systems LECTURE 6 Stack

16. SG6 : FIT1001 Computer Systems S1 2006 16 Hardware Stack contiguous block of memory locations  to store values have a pointer to value on “top” of stack –pointer is typically a register in processor, e.g. SP PUSH –puts new value on top of stack >modifies memory and SP POP –removes value from top of stack >modifies SP only LIFO storage Last In is the First Out

17. SG6 : FIT1001 Computer Systems S1 2006 17 Stack Example X SP X Y X Y top of stack LIFO: Y is Last In and First Out ??? initially empty PUSHX PUSH Y POP

18. SG6 : FIT1001 Computer Systems S1 2006 18 Use of Stack to Save Return Addresses RETURN pop return address off top of stack and put into PC ! CALL push address of next instruction onto top of stack and then set PC = address of Proc 4000 4500 4800 4601 4800 4651 4101 address of instruction AFTER “call” to Proc1

19. www.monash.edu.au FIT1001- Computer Systems LECTURE 6 Interrupts

20. SG6 : FIT1001 Computer Systems S1 2006 20 Interrupts Signal that causes the CPU to alter its normal flow on instruction execution –frees CPU from waiting for events –provides control for external input Examples –Completion of an I/O process –unexpected input –abnormal situation (catastrophes - power failure) –detection of a hardware failure –illegal instructions / error handling –multitasking, multiprocessing

21. SG6 : FIT1001 Computer Systems S1 2006 21 The CPU - The Interrupt Cycle  Fetch / Execute cycle  Interrupt cycle HALT START Fetch Next Instruction Execute Instruction Check/Process Interrupt Interrupts Disabled

22. SG6 : FIT1001 Computer Systems S1 2006 22 Instruction Cycle to Process Interrupts

23. SG6 : FIT1001 Computer Systems S1 2006 23 Interrupt Types In general interrupts can be grouped into three categories –Processor Interrupts >Internal Hardware Interrupts >Error, stack overflow or protection violations –Hardware Interrupts >External Hardware Interrupts –Software Interrupts >Special instructions

24. SG6 : FIT1001 Computer Systems S1 2006 24 Interrupt Terminology Interrupt lines (hardware) Interrupt request Interrupt handlers –Program that services the interrupt –Also known as an interrupt routine Process Control Block (PCB) –Located in a part of memory known as the stack area –All registers of a program are saved here before control is transferred to the interrupt handler

25. SG6 : FIT1001 Computer Systems S1 2006 25 Servicing the interrupt –suspends program in progress –saves pertinent information including last instruction executed and data values in registers in the PCB (process control block) –branches to interrupt handler Interrupt Terminology

26. SG6 : FIT1001 Computer Systems S1 2006 26 Simple Interrupt Processing

27. SG6 : FIT1001 Computer Systems S1 2006 27 Servicing an Interrupt

28. SG6 : FIT1001 Computer Systems S1 2006 28 Use of Interrupts Notify that an external event has occurred –real-time or time-sensitive Signal completion –printer ready or buffer full Allocate CPU time –time sharing Indicate abnormal event (CPU originates for notification and recovery) –illegal operation, hardware error Software interrupts

29. SG6 : FIT1001 Computer Systems S1 2006 29 Multiple Interrupts Identifying devices –Polling (checking for input in rotation) –Vectored interrupts (include address of interrupting device) Interrupt priorities –Loss of data vs. task completion Maskable (disabled) interrupts

30. SG6 : FIT1001 Computer Systems S1 2006 30 Vectored Interrupts

31. SG6 : FIT1001 Computer Systems S1 2006 31 Polled Interrupts

32. SG6 : FIT1001 Computer Systems S1 2006 32 Multiple Interrupts Example

33. www.monash.edu.au FIT1001- Computer Systems LECTURE 6 Real World Architectures

34. SG6 : FIT1001 Computer Systems S1 2006 34 Real World Architectures MARIE shares many features with modern architectures but it is not an accurate depiction of them. In the following slides, we briefly examine two machine architectures. We will look at an Intel architecture, which is a CISC machine and MIPS, which is a RISC machine. –CISC is an acronym for complex instruction set computer. –RISC stands for reduced instruction set computer.

35. SG6 : FIT1001 Computer Systems S1 2006 35 Real World Architectures The classic Intel architecture, the 8086, was born in 1979. It is a CISC architecture. It was adopted by IBM for its famed PC, which was released in 1981. The 8086 operated on 16-bit data words and supported 20-bit memory addresses. Later, to lower costs, the 8-bit 8088 was introduced. Like the 8086, it used 20-bit memory addresses. What was the largest memory that the 8086 could address?

36. SG6 : FIT1001 Computer Systems S1 2006 36 Real World Architectures The 8086 had four 16-bit general-purpose registers that could be accessed by the half-word. It also had a flags register, an instruction register, and a stack accessed through the values in two other registers, the base pointer and the stack pointer. The 8086 had no built in floating-point processing. In 1980, Intel released the 8087 numeric coprocessor, but few users elected to install them because of their cost.

37. SG6 : FIT1001 Computer Systems S1 2006 37 Real World Architectures In 1985, Intel introduced the 32-bit 80386. It also had no built-in floating-point unit. The 80486, introduced in 1989, was an 80386 that had built-in floating-point processing and cache memory. The 80386 and 80486 offered downward compatibility with the 8086 and 8088. Software written for the smaller word systems was directed to use the lower 16 bits of the 32-bit registers.

38. SG6 : FIT1001 Computer Systems S1 2006 38 Real World Architectures Currently, Intel’s most advanced 32-bit microprocessor is the Pentium 4. It can run as fast as 3.06 GHz. This clock rate is over 350 times faster than that of the 8086. Speed enhancing features include multilevel cache and instruction pipelining. Intel, along with many others, is marrying many of the ideas of RISC architectures with microprocessors that are largely CISC.

39. SG6 : FIT1001 Computer Systems S1 2006 39 Real World Architectures The MIPS family of CPUs has been one of the most successful in its class. In 1986 the first MIPS CPU was announced. It had a 32-bit word size and could address 4GB of memory. Over the years, MIPS processors have been used in general purpose computers as well as in games. The MIPS architecture now offers 32- and 64-bit versions.

40. SG6 : FIT1001 Computer Systems S1 2006 40 Real World Architectures MIPS was one of the first RISC microprocessors. The original MIPS architecture had only 55 different instructions, as compared with the 8086 which had over 100. MIPS was designed with performance in mind: It is a load/store architecture, meaning that only the load and store instructions can access memory. The large number of registers in the MIPS architecture keeps bus traffic to a minimum. How does this design affect performance?

41. SG6 : FIT1001 Computer Systems S1 2006 41 Real World Architectures The Intel architecture is an example of a CISC architecture MIPS is an example of a RISC architecture

42. SG6 : FIT1001 Computer Systems S1 2006 42 Next… (remove for next week) Indicates what is coming up in the next lecture in that week! This slide can be removed if the last lecture in the week and replaced with the next slide.

43. SG6 : FIT1001 Computer Systems S1 2006 43 Next Week….(remove if 1st or 2 nd lecture) Only need for last lecture in week…