1. OIF SPI System Packet Interface
Applied Micro Circuits Corporation

2. Receive Link Layer Device Framer Interface (TFI)
OIF Electrical Specifications
Status
Transmit Link Layer Device
Receive Link Layer Device
System Packet
Interface (SPI)
Data
SERDES Framer
Interface (SFI)
FEC
Data
Clock
SERDES Framer
Interface (SFI)
Optical
Interface
SERDES Device
and
Optics
Data
Clock
Data
T F I
PHY
Device
TDM Fabric to
Framer Interface (TFI) OR

3. System Packet Interface (SPI-n)
S y s t e m t o O p t i c s
System Packet
Interface (SPI)
Transmit
Interface
Transmit Link Layer Device
Receive Link Layer Device
PHY
Device
Data
Status
Data
Status
Receive
Interface
O p t i c s t o S y s t e m

4. SPI-3: OIF SPI3-01.0
S y s t e m t o O p t i c s TX
TXREFCK
TXREFCK
TFCLK
Link
Layer NP
ATM
SAR
TDATA [31:0]
Framer C D
TENB
TXDATA [15:0]
Serdes
TMOD[1:0]
TPRTY
TXDSC
TSOP
TEOP
TXDCK
TERR
TSX
TXCKSRC
DTPA[3:0]
SONET/SDH
OC-48
4xOC-12
16xOC-3 B A
STPA
PTPA
TADR[1:0]
RXDATA [15:0]
RXDSC
RFCLK
RENB
RXDCK
RDAT[31:0]
RMOD[1:0] B A
RRPRTY
RXS
RVAL
RSOP
REOP
RXREFCK
RERR
RSX RX
RXREFCK
O p t i c s t o S y s t e m
Support up to 2.5Gb/s bi-directional data throughput
8 bit or 32 bit interface options
LVCMOS signals; point to point operation
In-band addressing

5. SPI-3: OIF SPI3-01.0 8 bit operation supports 1xOC-12 (622 MB/s)
S y s t e m t o O p t i c s TX
TXREFCK
TXREFCK
TFCLK
Link
Layer NP
ATM
SAR
TDATA [31:0]
Framer C D
TENB
TXDATA [15:0]
Serdes
TMOD[1:0]
TPRTY
TXDSC
TSOP
TEOP
TXDCK
TERR
TSX
TXCKSRC
DTPA[3:0] B A
STPA
Supports:
Packet over SONET
ATM over SONET
Frame Relay over SONET
PTPA
TADR[1:0]
RXDATA [15:0]
RXDSC
RFCLK
RENB
RXDCK
RDAT[31:0]
RMOD[1:0] B A
RPRTY
RXS
RVAL
RSOP
REOP
RXREFCK
RERR
RSX RX
RXREFCK
O p t i c s t o S y s t e m
8 bit operation supports 1xOC-12 (622 MB/s)
Data transfer independent of line bit rate
Transfers ATM cells, packets including IP, FR, etc.
Flow control on interface
Error indication signal

6. SPI-4 Phase 1: OIF-SPI4-01.0
S y s t e m t o O p t i c s TX
TXREFCK
TXREFCK
TXCLK
Link
Layer NP
ATM
SAR
TXDATA [63:0]
Framer C D
TXADDR[N-1:0]
TXDATA [15:0]
Serdes
TXSIZE[2:0]
TXPRTY[3:0]
TXDSC
TXSOCP
SONET/SDH
OC-192
10GE WAN/LAN
4xOC-48
16xOC-12
64xOC-3
256xSTS-1
TXEOP
TXDCK
TXERR
TXVALID
TXCKSRC
TXSTART
TXFULL[3:0] B A
RXDATA [15:0]
RXCLK
RXDATA[63:0]
RXDSC
RXADDR[N-1:0]
RXSIZE[2:0]
RXDCK
RXPRTY[3:0] B A
RXSOCP
RXS
RXEOP
RXERR
RXVALID
RXSTART
RXREFCK
RXFULL[3:0] RX
RXREFCK
O p t i c s t o S y s t e m
Support up to 10GB/s bi-directional data throughput
First generation; 200 MHz operation implementable in FPGA technology
64 bit 200 MHz (lower rate operation supported)
HSTL Class 1 signals; source synchronous clocking; point to point operation
Out-of-band addressing

7. SPI-4 Phase 1: OIF-SPI4-01.0
S y s t e m t o O p t i c s TX
TXREFCK
TXREFCK
TXCLK
Link
Layer NP
ATM
SAR
TXDATA [63:0]
Framer C D
TXADDR[N-1:0]
TXDATA [15:0]
Serdes
TXSIZE[2:0]
TXPRTY[3:0]
Supports:
POS/HDLC
EoS/X.86
ATM
10GE LAN
10GE WAN
TXDSC
TXSOCP
TXEOP
TXDCK
TXERR
TXVALID
TXCKSRC
TXSTART
TXFULL[3:0] B A
RXDATA [15:0]
RXCLK
RXDATA[63:0]
RXDSC
RXADDR[N-1:0]
RXSIZE[2:0]
RXDCK
RXPRTY[3:0] B A
RXSOCP
RXS
RXEOP
RXERR
RXVALID
RXSTART
RXREFCK
RXFULL[3:0] RX
RXREFCK
O p t i c s t o S y s t e m
4x16bit mode of operation for 4xOC-48 multi-phy applications
Supports Packet over SONET (POS); Ethernet over SONET (EoS/X.86);
ATM over SONET; 10GE WAN/LAN PHY (IEEE 802.3ae)

8. SPI-4 Phase 2 Support up to 10GB/s bi-directional data throughput
S y s t e m t o O p t i c s
TXREFCK
TXREFCK TX
Link
Layer NP
ATM
SAR
Framer C D
SONET/SDH
OC-192
10GE WAN/LAN
4xOC-48
16xOC-12
64xOC-3
256xSTS-1
TXDATA [15:0]
Serdes
TDCLK
TDAT [15:0]
TXDSC
TCTL
TXDCK
TSCLK
TXCKSRC
TSTAT[1:0] B A
RXDATA [15:0]
RXDSC
RXDCK
RDCLK
RDAT[15:0] B A
RCTL
RXS
RSCLK
RSTAT[1:0]
RXREFCK RX
RXREFCK
O p t i c s t o S y s t e m
Support up to 10GB/s bi-directional data throughput
Next generation technology; faster and narrower interface
16 bit LVDS 800 MHz (622 MHz minimum operation)

9. SPI-4 Phase 2: OIF-SPI4-02.0
S y s t e m t o O p t i c s
TXREFCK
TXREFCK C D TX
Link
Layer NP
ATM
SAR
Framer
TXDATA [15:0]
Serdes
TDCLK
TDAT [15:0]
TXDSC
TCTL
Supports:
POS/HDLC
EoS/X.86
ATM
10GE LAN
10GE WAN
TXDCK
TSCLK
TXCKSRC
TSTAT[1:0] B A
RXDATA [15:0]
RXDSC
RXDCK
RDCLK
RDAT[15:0] B A
RCTL
RXS
RSCLK
RSTAT[1:0]
RXREFCK RX
RXREFCK
O p t i c s t o S y s t e m
Supports Packet over SONET (POS); Ethernet over SONET (EoS/X.86); ATM over SONET; 10GE WAN/LAN PHY (IEEE 802.3ae)
FIFO status out of band; 2 options for status signal rate
(full and 1/4 speed)

10. SPI-5: OIF-SPI5-01.0 System Packet Interface
Interface (SPI)
SERDES Framer
Interface (SFI-5)
Transmit
Interface
Transmit Link Layer Device
Receive Link Layer Device
PHY
Device
Data
SERDES
Device
Status
Data
Status
Receive
Interface
OC-768 System Interface for Physical and Link Layer Devices

11. SPI-5: OIF-SPI5-01.0 System Packet Interface
Transmit Interface
PHY
Device
Transmit Link Layer Device
TDCLK
TDAT [15:0]
Point-to-point
connection
TCTL
Support for
256 ports
TSTAT
Receive Link Layer Device
RDCLK
RDAT [15:0]
RCTL
RSTAT
Receive Interface
Point-to-point connection (i.e. single PHY / single Link Layer device)
Support for 256 ports with address extension to 2144 ports

12. SPI-5: OIF-SPI5-01.0 System Packet Interface
Transmit Interface
PHY
Device
Transmit Link Layer Device
TDCLK
TDAT [15:0]
TCTL
2.488 Gb/s
TSTAT
Receive Link Layer Device
RDCLK
RDAT [15:0]
RCTL
RSTAT
Receive Interface
Control words carry In-band Port Address, start/end of packet indication & error-control mode
Data transfer segmented in bursts that are multiples of 16 words (32 bytes)
2.488 Gb/s minimum data rate per line on data path

13. SPI-5: OIF-SPI5-01.0 System Packet Interface
Transmit Interface
PHY
Device
Transmit Link Layer Device
TDCLK
TDAT [15:0]
TCTL
TSTAT
Receive Link Layer Device
RDCLK
RDAT [15:0]
RCTL
RSTAT
Receive Interface
Independent transmit/receive pool status channel
Operates at the same clock rate as the data path

14. SPI-5: OIF-SPI5-01.0 System Packet Interface
Anatomy of a Transfer
Max
16 bytes
Address Control Word
Optional
Address Data Word(s)
Payload Control Word
32n Bytes (except
End-of-Packet Transfers)
Payload
Data
Words
Control Word