1. 1 CSE370, Lecture 15 Lecture 15 u Logistics n HW5 due this Friday n HW6 out today, due Friday Feb 20 n I will be away Friday, so no office hour n Bruce Hemingway will teach the class. u Last lecture n Memory storage elements íFlip-flops and latches n State diagrams u Today n Finish flip-flops and latches n Registers n Counters n Start of Finite State Machine design (FSM)

2. 2 CSE370, Lecture 15 The “WHY” slide u Registers and Counters n Registers and counters are very simple yet powerful examples of how you can use the basic memory elements to conduct productive behavior. They are used everywhere in a computer.

3. 3 CSE370, Lecture 15 How do we make a D flip flop? Q D Clk W Y X Z Q’ When Clk  0 then Y (set for SR-latch block ) becomes Z’=D and X (reset for SR-latch block) becomes W’=D’ so Q becomes D This is stable until D or the Clk switches If Clk=1 then X=Y=0 and SR-latch block holds previous values of Q,Q’ also Z=D’ and W=Z’=D While Clk=0, if D switches then Z becomes 0 and X and W hold their previous values and Y=X’=D as before. Falling edge-triggered flip-flop

4. 4 CSE370, Lecture 15 Terminology & notation DQ Q CLK Input Output Falling-edge triggered D flip-flop DQ Q CLK Input Output Rising-edge triggered D flip-flop DQ Q CLK Input Output Negative D latch DQ Q CLK Input Output Positive D latch

5. 5 CSE370, Lecture 15 behavior is the same unless input changes while the clock is high CLK D Q ff Q latch Latches versus flip-flops DQ Q CLK DQ Q

6. 6 CSE370, Lecture 15 The master-slave D DQ CLK Input Master D latch DQ Output Slave D latch master-slave D flip-flop

7. 7 CSE370, Lecture 15 CLK D Q ff Q latch’ Q masterslave Master-Slave D implements D flip-flop DQ Q CLK DQ Q

8. 8 CSE370, Lecture 15 T flip-flop u Full name: Toggle flip-flop u Output toggles when input is asserted n If T=1, then Q  Q' when CLK  n If T=0, then Q  Q when CLK  CLK Q TQ > Input(t) Q(t) Q(t +  t) 000 011 101 110 Input

9. 9 CSE370, Lecture 15 Clear and preset in flip-flops u Clear and Preset set flip-flop to a known state n Used at startup, reset u Clear or Reset to a logic 0 n Synchronous: Q=0 when next clock edge arrives n Asynchronous: Q=0 when reset is asserted íDoesn't wait for clock íQuick but dangerous u Preset or Set the state to logic 1 n Synchronous: Q=1 when next clock edge arrives n Asynchronous: Q=1 when reset is asserted íDoesn't wait for clock íQuick but dangerous RS DQ

10. 10 CSE370, Lecture 15 Registers u Group of storage elements read/written as a unit. n Store related values (e.g. a binary word) u Collection of flip-flops with common control n Share clock, reset, set lines u Example: n Storage registers n Shift registers n Counters

11. 11 CSE370, Lecture 15 Storage registers u Basic storage registers use flip flops u Example: 4 bit storage register RSRS DQDQDQ OUT1OUT2OUT3OUT4 CLK IN1IN2IN3IN4 RS RS DQ "0"

12. 12 CSE370, Lecture 15 Shift registers u Hold successively sampled input values n Delays values in time n Example: 4-bit shift register íStores 4 input values in sequence DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK

13. 13 CSE370, Lecture 15 Shift-register applications u Parallel-to-serial conversion for signal transmission u Pattern recognition (circuit recognizes 1001) DQDQDQDQ IN CLK OUT parallel inputs parallel outputs serial transmission CLK

14. 14 CSE370, Lecture 15 DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK Counters u Ring counter: Sequence is 1000, 0100, 0010, 0001 n Assuming one of these patterns is the starting state u Johnson counter: Sequence is 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK

15. 15 CSE370, Lecture 15 A binary counter u Has logic between flip-flops Flip low-order bit each clock cycle Flip next bit in cycle when low- order bit is 1 Flip next bit when both lower order bits are 1 Flip next bit when all lower order bits are 1

16. 16 CSE370, Lecture 15 Combinational Logic Storage Elements Outputs State OutputsState Inputs Inputs “States” for finite state machines are kept in the storage elements u Combinational logic and storage elements n Localized feedback loops n Choice of storage elements alters the logic

17. 17 CSE370, Lecture 15 In = 0 In = 1 In = 0In = 1 100 010 110 111 001 Finite-state machines (FSMs) u States: Possible storage-element values u Transitions: Changes in state n Clock synchronizes the state changes u Sequential logic n Sequences through a series of states n Based on inputs and present state

18. 18 CSE370, Lecture 15 100 110 111 011 101010 000 001 0 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 DQDQDQ IN OUT1OUT2OUT3 CLK Drawing state diagrams u Show input values on transition arcs u Show output values in state nodes

19. 19 CSE370, Lecture 15 010 100 110 011 001 000 101 111 3-bit up-counter Counters revisited u Great simple examples of state machines n Output is the counter’s state u Next state is well defined n Does not depend on input (no inputs)

20. 20 CSE370, Lecture 15 FSM design procedure (using counters) 1. Draw a state diagram 2. Draw a state-transition table 3. Encode the next-state functions n Minimize the logic using k-maps 4. Implement the design We will use a ‘3-bit up counter’ as an example

21. 21 CSE370, Lecture 15 1. Draw a state diagram 010 100 110 011 001 000 101 111 3-bit up-counter

22. 22 CSE370, Lecture 15 2. Draw a state-transition table u Like a truth-table n State encoding is easy for counters  Use count value current statenext state 00000011 10010102 20100113 30111004 41001015 51011106 61101117 71110000

23. 23 CSE370, Lecture 15 3. Encode the next state functions u Assume D flip-flops as state elements C3C2C1N3N2N1 000001 001010 010011 011100 100101 101110 110111 111000 0011010100110101 C2 C3 C1 N3 1111000011110000 C2 C3 C1 N1 0110100101101001 C2 C3 C1 N2 N1:= C1' N2:= C1C2' + C1'C2 := C1 xor C2 N3:= C1C2C3' + C1'C3 + C2'C3 := C1C2C3' + (C1' + C2')C3 := (C1C2) xor C3

24. 24 CSE370, Lecture 15 4. Implement the design u 3 flip-flops hold state n Counter is synchronously clocked u Minimized logic computes next state