1. On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits Department of Electrical and Computer Engineering By Han Lin Jiun-Yi Lin 05/14/2014

2. Overview  Introduction  Principle and background  Proposed reliability monitor circuit  Circuit Blocks and Simulation Result:  Ring Oscillator  Phase Comparator  Majority Voting Circuit  Beat Frequency Detector  8 Bit Counter Circuit  Total Circuit  Conclusion 05/14/2014 1

3. Abstract Precise measurement of digital circuit degradation caused by aging Reliability monitor using beat frequency of two ring oscillators to get a high sensing resolution 1V, 32nm CMOS technology, up to 0.02% sensing resolution

4. Overview  Introduction  Principle and background  Proposed reliability monitor circuit  Circuit Blocks and Simulation Result:  Ring Oscillator  Phase Comparator  Majority Voting Circuit  Beat Frequency Detector  8 Bit Counter Circuit  Total Circuit  Conclusion 05/14/2014 1

5. Types of reliability issues BTI (bias temperature instability) HCI (hot carrier injection) TDDB (time-dependent dielectric breakdown) NBTI (negative bias temperature instability) NBTI effect is among the most pressing issues among all of them

6. Cause of NBTI effect Structural mismatch at the Si-SiO 2 interface cause dangling bonds Si-H bonds is transformed by hydrogen passivation process of dangling Si bonds which is made by oxidation of Si-SiO 2 Broken bonds from Si-H degrade the driving current of pMOS threshold voltage Positive shift in absolute value of pMOS threshold voltage |Vtp| in stress phase Broken Si-H bonds is annealed in recovery phase, and Vtp is reduced

7. Cross section of pMOS device and pMOS Vth degradation

8. Constraints of typical measurement Device probing, on-chip ring oscillator frequency monitoring Limitations in sensing resolution, cannot get large number of data points

9. Simulation platform Microsoft Windows HSPICE 2009 CosmosScope

10. Overview  Introduction  Principle and background  Proposed reliability monitor circuit  Circuit Blocks and Simulation Result:  Ring Oscillator  Phase Comparator  Majority Voting Circuit  Beat Frequency Detector  8 Bit Counter Circuit  Total Circuit  Conclusion 05/14/2014 1

11. Beat frequency detection circuit

12. Measuring difference in frequency between Stressed and Reference ROSC When there is exactly one in the pulse difference between two ROSC, we can get the value of N before stress, and we use this method to get N’ which is detected after stress period.

13. Beat frequency detection scheme Using difference between stressed and reference ROSC Before stress: N/f ref =(N-1)/f stress After stress: N’/f ref =(N’-1)/f’ stress Percent of frequency degradation: (f’ stress -f stress )/f stress =(N’-N)/(N’(N-1))

14. Change in counter output by frequency degradation (f’ stress -f stress )/f stress =(N’-N)/(N’(N-1)) When there is 1% degradation, N will decrease half compared with 1% for convention method

15. Architecture of silicon odometer Two ring oscillators, identical structure, different Vdd Phase comparator will show frequency difference between two ROSC. 5-bit majority voting circuit can erase the bubbles caused by jitter effect from phase comparator Beat frequency detector can produce a DETECT signal to reset the counter, and get the output from the register

16. Block diagram

17. Overview  Introduction  Principle and background  Proposed reliability monitor circuit  Circuit Blocks and Simulation Result:  Ring Oscillator  Phase Comparator  Majority Voting Circuit  Beat Frequency Detector  8 Bit Counter Circuit  Total Circuit  Conclusion 05/14/2014 1

18. Ring Oscillator 05/14/2014 3

19. Simulation Result of Ring Oscillator Circuit 05/14/2014 4 The ring oscillator has a period of 4 ns

20. Phase Comparator 05/14/2014 5 CLK=0 Pre charge CLK=1 Evaluate (Compare the phase of A and B) CLK=1 A’&&B=1 PC_OUT=1 CLK=1 A’&&B=0 PC_OUT=0 CLK=0 PC_OUT keep the same value X: Pre charge Switch open Switch close

21. Simulation Result of Phase Comparator Circuit 05/14/2014 6 CLK=1 A’&&B=1 PC_OUT=1 CLK=0 PC_OUT keep the same value CLK=1 A’&&B=0 PC_OUT=0

22. Majority Voting Circuit 05/14/2014 7

23. Majority Voting circuit (Continue) 05/14/2014 8

24. Simulation Result of Majority Voting Circuit 05/14/2014 9 PC_OUT 10111010 VOTE_OUT 11111100 10111011 111111 00

25. Beat Frequency Detector 05/14/2014 10

26. Simulation Result of Beat Frequency Detector Circuit 05/14/2014 11 Beat Frequency Latency 10111 011 111111 00

27. 8 Bit Counter Circuit 05/14/2014 12

28. Simulation Result of 8 Bit Counter 05/14/2014 13

29. Simulation Result of Total Circuit 05/14/2014 14

30. 15 CONCLUSION ■ 05/14/2014

31. 16 05/14/2014 THANK YOU!