1. Design And Implementation Of Frequency Synthesizer And Interrogating Phase Noise In It's Parts Advisor Professor : Dr.Sadr & Dr.Tayarani Students: Majid Sodagar Mehran Mohammadi Izad In The Name Of God

2. Brief Review Introduction Block Diagrams Models –Oscillator –Divider –Charge Pump Design And Measurements Conclusions

3. Signals Suffer From Noise !

4. Introduction & Motivation The GSM system needs very narrow channel spacing Thus low phase noise levels are required. e.g., At 1 kHz from the carrier, a single sided spectral noise density of -80 dBc/Hz

5. Conventional Synthesizer Block Diagram

6. PLL Block Diagram And Noise Sources

7. Transfer Functions

8. Typical Superposition Of All Sources

9. Fractional Synthesizer Block Diagram

10. Noise Shaping First Order Delta Sigma Modulator Higher Order Filter Order :

11. Fractional Synthesizer Characteristic Fast settling High resolution synthesis becomes possible giving greater design flexibility at the system level. Needs Compensation Circuitry For The Fractional Spur

12. Oscillator Noise Modeling LTI Model (Leeson-Cutler) - Ignoring Time Variance Nature of Oscillator LTV Model (Hajimiri-Lee) - Take the Time Variance Nature of Oscillator into account.

13. Typical LC Oscillator A = Excess noise Factor N = For Active Inductor

14. LTI Model Using Only Z(s) of tank circuit

15. Typical Phase Noise Slopes Close to Career

16. LTV Model Every oscillator is a quasi periodic system the noise analysis should take this into account Model Benefits: –Design Aspects –Cyclostationary noise

17. Impulse Response The constant q max = CV peak is simply a normalization constant, the peak charge in the oscillator.

18. Graphical Interpretation

19. Divider Block Model

20. Divider Noise Model

21. Filter Noise Ignoring Thermal noise of Passive elements And Current Noise

22. Typical OpAmp Input Voltage Noise Our OpAmp Performance (OP27):

23. Charge Pump PFD Structure Lead And Lag Detection Increasing Lock Range Reduction of cycle slipping

24. Effects Of CP PFD On Phase Noise Effect of Leakage On reference Spurs –Charge pump is off majority of the Time –Leakage causes VCO tuning voltage to change Effect of Mismatch On reference Spurs –The width of correction pulses is related to the mismatch –causes the AC voltages undesirable AC voltages Causes FM modulation

25. Experimental Results for FM modulation (Spurs) Reference Spur example

26. CP Phase noise model Where –F c = Flicker Corner Frequency –F m = Offset From Carrier –I 0 = current noise Floor

27. Stability problem In CP PLL The charge pump nature is discrete so it is prone to instability The following condition should be satisfied to use continuous time analysis !!

28. Our Design

29. Design Specification Design for GSM requirements –Fref = 10MHz –Fcomp = 200KHz –LoopBandWidth = 15KHz –RFOut = 800 – 1100 MHz –PhaseMargin = 45 deg

30. Schematic

31. Active Filter

32. Simulated Open Loop Response

33. Passive Phase Noise Result @1KHz Phase noise = -53.7-10log(200) = -76.7 dBc/Hz

34. Passive Phase Noise Result @10KHz Phase noise = -51.9-10log(200) = -74.9 dBc/Hz

35. Passive Phase Noise Result @100KHz Phase noise = -70.2-10log(500) = -92.9 dBc/Hz

36. Step Response And Lock Time Settling time = 150  sec

37. Active Phase Noise Result @1KHz Phase noise =-55.1-10log(200)= -78.1 dBc/Hz

38. Active Phase Noise Result @10KHz Phase noise =-49.7-10log(200)=-72.7 dBc/Hz

39. Inappropriate Opamp Bias !!! Causing excess noise near the career

40. 1Hz Normalize Phase Noise Good way for characterize the phase noise of PLL Assumes charge pump phase noise is dominant PN=PN1Hz+20logN+10log(Fcomp)

41. Experimental Result: For our design: –PN1Hz = -205 dBc/Hz –N = 4500 –Fcomp = 200KHz –PN =-205+20log(4500) +10log(200KHz) = -78.9 dBc/Hz

42. Conclusions By using better synthesizer, its possible to achieve lower Phase noise If the CP noise Dominates in the circuit, then we can not detect the effect of Active filter noise

43. Any Question?

44. Thanks