1. Radiation Hardness Test Chip Matthias Harter, Peter Fischer Uni Mannheim

2. LS Schaltungstechnik & Simulation CBM Meeting DresdenRad. Hard. TestChip2 Overview 1.Reminder: Radiation Damage & Remedies 2.Chip description 3.First results Note: Not yet clear how much rad. hardness we need for CBM... This little work is just a contribution to discussions...

3. LS Schaltungstechnik & Simulation CBM Meeting DresdenRad. Hard. TestChip3 Radiation Damage – very superficial  Ionizing radiation leads to positive charges in thick oxides  Threshold voltage shift – decreasing for NMOS  leakage ‘around’ NMOS  creation of parasitic NMOS (field oxide) PMOS remains unaffected.  Large local charge deposition can lead to SET: single event transient = spike on signal SEU: single event upset = bit flip SEGR: single event gate rupture (really?)

4. LS Schaltungstechnik & Simulation CBM Meeting DresdenRad. Hard. TestChip4 Remedies  Enclosed NMOS (other shapes are possible!)  Guard rings between NMOS with drains on different potential  Special FF design / redundancy / voting / hamming... for SEU / SET  Consequences: need special extraction files larger area (x4 for digital designs) larger caps -> often more power in digital (x4) Hard to make good NMOS current source (large L no possible) Hard to make good NMOS switches (very asymmetric & large caps)

5. LS Schaltungstechnik & Simulation CBM Meeting DresdenRad. Hard. TestChip5 Example: radhard MUX2->1  Our ‘mixed mode’ lib uses separate nets for digital wells (nwell, pwell) Digital PMOS: vddd! Digital NMOS: gndd! PWELL NMOS: gndb! NWELL PMOS: vddb! Guard rings Enclosed NMOS

6. LS Schaltungstechnik & Simulation CBM Meeting DresdenRad. Hard. TestChip6 Radhard vs. Normal Layout  We want to compare both types. Therefore made cells with equal transistor / layout size: Hard Normal

7. LS Schaltungstechnik & Simulation CBM Meeting DresdenRad. Hard. TestChip7 Test Chip  Goals: Verify models (speed) Measure SEU during irradiation Measure leakage after irradiation for ‘hard’ and ‘non-hard’ layouts Keep chip very simple for easy testing with minimal equipment  Circuits: 1 ring oscillator with 101 inverters & enable. Sim. frequency: 176 MHz 8 normal shift registers, 16 Bit, common data input, one output via 8-1 MUX 16 linear feedback shift registers (LFSR) producing pseudo random bit sequences, 16 bit long. Test equality of all 16 LFSRs to detect SEU. Rad hard output drivers. All pads have ESD protection diodes

8. LS Schaltungstechnik & Simulation CBM Meeting DresdenRad. Hard. TestChip8 Radhard vs. Normal Layout  Chip is implemented twice: 1.radhard with round NMOS + guard rings 2.Normal Layout. Widths of MOS are same as for round devices  Identical pinout!  17 pins per side (just one side of a JLCC68)  Switch between the two versions by rotating carrier in socket! radhard version (pads at inner side) normal Version (edge of die) 123...17 123...17

9. LS Schaltungstechnik & Simulation CBM Meeting DresdenRad. Hard. TestChip9 Test Chip Layout could cut here Another project.. This chip

10. LS Schaltungstechnik & Simulation CBM Meeting DresdenRad. Hard. TestChip10 Detail of pinout… DoutSRmuxOscOutLFSReqDoutLFSR SRsel gndd!vddd!vddb!gndb!clkDinSRresetNOscEngndd! 1.8 V optional SRsel selects shift register to send to DoutSRmux 3 176 MHz OscEn SRsel 16x 8x 16x clk DinSR resetN 16x = ? LFSReq resetN clk DinSR is the input of all shift registers LFSReq shows that all LFSRs have same output 1241415 56789101117

11. LS Schaltungstechnik & Simulation CBM Meeting DresdenRad. Hard. TestChip11 Measurements: Ring Oscillator  Works as expected.  Simulated speed: 176MHz  Measured: Supply [V]Speed [MHz] 1.8150 1.7140 1.6130 1.5117 1.278 1.051 1.8V 1.0V

12. LS Schaltungstechnik & Simulation CBM Meeting DresdenRad. Hard. TestChip12 Measurements: LFSR  Works as expected  Produces nice spectrum on Analyzer... after reset output reset clocked @ 120MHz

13. LS Schaltungstechnik & Simulation CBM Meeting DresdenRad. Hard. TestChip13 Problems & Summary  Shift registers also work as expected  Problem: Large supply current. May be setup but more likely wrong type of substrate connection somewhere...  Good agreement in speed. Must check voltage dependence.  Next steps: Decide if irradiation of this is interesting May resubmit in 3 weeks if there is a bug. May increase register length.