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ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Under-project Meeting Network-on-Chip Group 2007/3/07 TA: 林書彥 黃群翔.

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Presentation on theme: "ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Under-project Meeting Network-on-Chip Group 2007/3/07 TA: 林書彥 黃群翔."— Presentation transcript:

1 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Under-project Meeting Network-on-Chip Group 2007/3/07 TA: 林書彥 黃群翔

2 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 2 [1][1] More and More on A Chip……. Now up to 80 cores!!

3 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 3 Network-on-Chip  Under-project  Project#1: Topology Mapping  Project#2: Routing Algorithm

4 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 4 Project#1: Topology Mapping  Mapping on 2D-Mesh [2] ( X ) long distance ( O ) short distance

5 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 5 Project#2: Routing on NoC (1)  Routing - determine the paths from S to D ( X ) contentious ( O ) balanced How to transmit????

6 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 6 Performance of NoC  Better routing/mapping on NoC can be…  Contention ↓  Latency ↓ (X)(O)

7 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 7 About This Semester….  Required Ability  C++ programming (Heavy!!)  Probability (optional)  Imagination  Working Items  Paper survey (Discussion biweekly)  Platform simulation  C++ for #1 mapping  SystemC for #2 routing  Repeat experiments  Advanced – create new algorithm!!!

8 ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 8 References 1.BONE, http://ssl.kaist.ac.kr/ocn/.http://ssl.kaist.ac.kr/ocn/ 2.Jingcao Hu and Radu Marculescu, “Energy- and Performance- Aware Mapping for Regular NoC Architecture,” IEEE Trans. On Computer-Aided Design of Integrated and Systems, Vol. 24, No.4, April 2005 3.D. Bertozzi et al., “Xpipes: A Network-on-Chip Architecture for Gigascale System-on-Chip,” IEEE Circuits and Systems Magazine, vol. 4, no. 2, 2004, pp. 18-31. 4.Y. K. Lien, “Application-Aware On-Chip Networking System Designfor SoC Applications.“ 國立台灣大學電子工程所碩士論文, June, 2006 5.C.J. Glass, L.M. Ni, “The Turn Model for Adaptive Routing,” Proceedings of The 19th Annual International Symposium Computer Architecture, pp.278 – 287, May 19-21, 1992 6.G.M. Chiu. “The odd-even turn model for adaptive routing,” IEEE Transactions on Parallel and Distributed Systems, vol. 11, pp. 729– 738,JULY 2000.

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