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Datta1 Routing for Reliability in Molecular Diode-based Programmable Nanofabrics Kushal Datta, Arindam Mukherjee and Arun Ravindran Department of Electrical.

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Presentation on theme: "Datta1 Routing for Reliability in Molecular Diode-based Programmable Nanofabrics Kushal Datta, Arindam Mukherjee and Arun Ravindran Department of Electrical."— Presentation transcript:

1 datta1 Routing for Reliability in Molecular Diode-based Programmable Nanofabrics Kushal Datta, Arindam Mukherjee and Arun Ravindran Department of Electrical and Computer Engineering University of North Carolina at Charlotte MAPLD 2005/1031

2 datta2 Nanofabric Architecture Switch Block Diode-based CMU Architecture NanoFabrics: Spatial Computing Using Molecular Electronics Seth Copen Goldstein and Mihai Budiu Proc. of The 28th Annual International Symposium on Computer Architecture, June 2001. Nano Block CMOS on Molecular: CMOL MAPLD 2005/1031

3 datta3 Circuit Primitives AB f = A. B AB f = A+B AB V dd f = A. B ff f MAPLD 2005/1031

4 datta4 Circuit Primitives AB V dd f = A+B A A A A V dd f MAPLD 2005/1031

5 datta5 Nano Electronic Design Automation An example Problem Formulation Given –A logic design –A nanofabric Constraints –Entry and exit directions of signals in nano/switch blocks –Size of nano and switch blocks Minimize –The total number of diodes and switches used  Improve robustness MAPLD 2005/1031

6 datta6 Nano EDA Flow Optimized Nano Layout Routing Space Search VHDL Code Boolean Function net list Decomposed List Packed List Placed Gate Array PKS + script Flow Map VPACK VPR Placed Nanofabric Alternate Routes Our IP optimizer Map FPGA Nanofabric MAPLD 2005/1031

7 datta7 Placement Use a standard algorithm of VPR and get a placed file. Modify the placed file. Modification of the placed file involves considering all the possible 12 transformations and deriving equations for them. Implement a mapping program for this. MAPLD 2005/1031

8 datta8 Placement Sample placed file Equations based on the transformation from the placed file for gate array to the placed file for the nano fabric: x = 2x – z y = 2y – z y A B C D E F G H 0 1 0 1 0 1 0 1 x Slice number (z) MAPLD 2005/1031

9 datta9 Global Routing Problem Formulation Required AND gate literals enter from West (W) side Required OR gate literals enter from North (N) side If (R (l i ) = W) & (E (l i )=N) 1 extra diode If (R (l i ) = N) & (E (l i )=W) 1 extra diode lili lili lili lili V dd MAPLD 2005/1031

10 datta10 Problem Formulation A C B S2S2 S1S1 l3l3 l2l2 l1l1 MAPLD 2005/1031

11 datta11 Future Design Flow VLSI-inspired Nano-EDA Bio-inspired Nano-EDA  High Fault Tolerance  Low Power Optimized Nano Layout Routing Space Search VHDL Code Boolean Function net list Decomposed List Packed List Placed Gate Array PKS + script Flow Map VPACK VPR Placed Nanofabric Alternate Routes Our IP optimizer Map FPGA Nanofabric MAPLD 2005/1031

12 datta12 Integrate Placement with Global and Detailed Routing - Improve Fault Tolerance Simulated Annealing Moves : –Select switch and nano blocks for placement –Select switch and nano blocks for global routing –Select entry and exit edges for global routing –Select exact entry and exit row/column in a block fro detailed routing MAPLD 2005/1031

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