1. 1 Strained-Si Devices and Circuits for Low-Power Applications 系所 : 積體電路研究所 指導教授 : 易序忠 教授 學號 :95662005 姓名 : 李俊志

2. 2 Outline Introduction Strained-S i Device Features Strained-S i CMOS inverter Strained-S i CMOS circuits Result and Discussion Conclusion References

3. 3 Introduction higher carrier mobility with preservation of conventional CMOS device structure and geometry, strained-Si (SS) MOSFETs are recently of much interest for highperformance circuit applications Due to the speed advantage, SS devices could be applied to low-power circuit by lowering supply voltage, one of the most effective ways for low-power circuit design.

4. 4 Strained-Si Device Features Based on the same technology node, strained-S i CMOS has the advantages of mobility enhancement to overcome the issues of mobility degradation due to scaling down.. To breakthrough the bottlenecks of the strained-S i CMOS technology - high quality S I G e virtual substrate formation and device structure design/integration including global and local strain, the platform of high performance CMOS process/device with mobility enhancement will be developed for the high-end S o C product.

5. 5 技術規格 :S i G e Virtual Substrate – thickness 70%, hole > 60% 技術特寫 : 高品質矽鍺虛擬基材的形成技術全面 與局部形變的元件結構設計及製程整合技術 競爭力：相容性佳：與 CMOS 製程相容 突破點：崁入 Si 、 SiC 中間層之 SiGe 虛擬基材形 成技術，有效降低其厚度

6. 6 Strained-Si CMOS Inverter

7. 7 The bulk-SS inverter is significantly fast VDD could be reduced by 85mv for the SS CMOS, which would decrease the static (DC) and (AC) power consumptions.

8. 8 圖一 Predicted delays per stage of unloaded 9-stageinverter ring oscillator for bulk-S i and bulk-SS devices

9. 9 For equal delay =15ps, DC power is ~20% lower in the SS device than the bulk-S i counterpart, Note that for equal VDD,DC power is comparable since V t is made equal, The lower VDD would yield less DIBL, thereby reducing I off and DC power.

10. 10 圖二 Predicted normalized static (DC) and dynamic (AC) power consumptions of the unloaded ring oscillator for bulk-S i and bulk-SS device in equal delay

11. 11 Strained-Si CMOS Circuits 圖三 Static 4-way NAND circuit with bulk-S i and bulk-SS device :dynamic power versus frequency and static power for (A.B.C.D)=(1.1.1.1),(1,1,1,0),(1,1,0,0),(1,0,0,0),(0,0,0,0)

12. 12 Result and Discussion DIBL: 長通道元件閘極下方的空乏區電荷 沿著源極到汲極呈現常數值的狀態分佈, 當汲極電壓增加時, 並不會影響其能帶的 分佈狀態.

13. 13 圖四 SI-SIO2 接面能帶圖

14. 14 圖五 DIBL 效應對輸出電阻的影響

15. 15 Conclusions

16. 16 References