1. Physical States for Bits

2. Black Box Representations

3. Truth Tables

4. Basic Logic Gates

5. NAND and NOR gates

6. Sum of Products Circuits

7. Timing Diagrams

8. Logic Levels for CMOS

9. The concept of voltage- controlled resistance

10. nMOS transistor

11. pMOS transistor

12. Now we put together nMOS and pMOS transistors to create an inverter

13. Switch Model for CMOS inverter

14. Logical operation of CMOS inverter

15. Explanation of 2-input CMOS NAND gate

16. Switch Model for NAND realized in CMOS

17. Explanation of CMOS NOR

18. CMOS NAND with 3 inputs

19. Example of realization of large NAND gates in CMOS

20. Buffers realized in CMOS

21. AND gate in CMOS

22. AND-OR-INVERT gate in CMOS

24. CMOS OR-AND-INVERT

26. Data Sheets and how to use them

27. Test Circuits and Waveforms

28. Input-Output Characteristics

29. Logic Levels and Noise Margins for CMOS logic family

30. Resistive Models of Inverters

31. Resistive model for CMOS LOW output with resistive load

32. Black Box Representations Resistive model for CMOS HIGH output with resistive load

33. Circuit defintions to calculate currents

34. Output loading specifications

35. Estimating sink and source currents

36. CMOS inverters with nonideal input voltages

37. Black Box Representations CMOS inverter with load and nonideal 1.5 voltage input

38. Black Box Representations CMOS inverter with load and nonideal 3.5 voltage input

39. What to do with non-used inputs?

40. Transition times

41. How to analyze transition times for CMOS output?

42. Model of HIGH-to-LOW transition

43. Fall time

44. Model of a CMOS Low-to-High Transition

45. Rise time for a LOW-to-HIGH transition of a CMOS Output

46. Propagation Delays for a CMOS inverter

47. Worst-Case Timing using logic-level boundary points

48. Ground bounce in an IC with eight inverters and one ground pin

49. CMOS transition gate

50. Two-input multiplexer using CMOS transmission gates

51. Schmitt-Trigger Inverter

52. Operation with slowly changing inputs

53. CMOS three-state buffers

54. Open-Drain CMOS NAND

55. Open-Drain CMOS NAND gate driving a load

56. Rising and Falling transitions of an open-drain CMOS output

57. Driving a LED with an open- drain output

58. Driving a LED with standard CMOS output

59. Eight Open-Drain Outputs driving a bus

60. Wired-AND function on three open-drain NAND-gate outputs

61. Two CMOS outputs trying to maintain opposite values on the same line

62. Black Box Representations Four open-drain outputs driving two inputs in the LOW state

63. Four open-drain outputs driving two inputs in the HIGH state

64. Input and output levels for CMOS devices using a 5V supply

65. Transfer characteristics of HC and HCT circuits

66. Speed and power characteristics of CMOS families operating at 5V

67. Input specifications for CMOS families with V CC between 4.5 V and 5.5V

68. Black Box Representations

91. ECL 2-input OR/NOR

92. Problems for quizzes

93. Black Box Representations