1. Chapter 1 Combinational CMOS Logic Circuits Lecture # 4 Pass Transistors and Transmission Gates

2. 2 Outline A Brief History CMOS Gate Design Pass Transistors CMOS Latches & Flip-Flops Standard Cell Layouts Stick Diagrams

3. CMOS Logic Structures Static logic circuits hold their output values indefinitely Dynamic logic circuits store the output in a capacitor, so it decays with time unless it is refreshed. We will look at a few of these structures

4. Pass Transistor Pass-transistor circuits are formed by dropping the PMOS transistors and using only NMOS pass transistors In this case, CMOS inverters (or other means) must be used periodically to recover the full V DD level since the NMOS pass transistors will provide a V OH of V DD – V Tn in some cases The pass transistor circuit requires complementary inputs and generates complementary outputs to pass on to the next stage

6. Signal Strength Strength of signal –How close it approximates ideal voltage source V DD and GND rails are strongest 1 and 0 nMOS pass strong 0 –But degraded or weak 1 pMOS pass strong 1 –But degraded or weak 0 Thus nMOS are best for pull-down network

7. Pass Transistors We have assumed source is grounded What if source > 0? –e.g. pass transistor passing V DD V g = V DD –If V s > V DD -V t, V gs < V t –Hence transistor would turn itself off nMOS pass transistors pull no higher than V DD -V tn –Called a degraded “1” –Approach degraded value slowly (low I ds ) pMOS pass transistors pull no lower than V tp

8. 8 Pass Transistors –The pass transistor is an nFET used as a switch-like element to connect logic and storage. –Used in NMOS; sometimes used in CMOS to reduce cost. –The voltage on the gate, V C, determines whether the pass transistor is “open” or “closed” as a switch. If V C = H, it is “closed” and connects V out to V in. If V C = L, it is “open” and V out is not connected to V in. –Consider V in = L and V in = H with V C = H. With V in = L, the pass transistor is much like a pull-down transistor in an inverter or NAND gate. So V out, likewise, becomes L. But, for V in = H, the output becomes the effective source of the FET. When V GS = V DD -V OUT =V Tn, the nFET cuts off. The H level is V OUT = V DD -V Tn. V in V out VCVC V C = 1 V C = 0

9. Pass Transistors Transistors can be used as switches

10. Pass Transistors Transistors can be used as switches

11. Pass Transistor This figure shows a simple XNOR implementation using pass transistors: If A is high, B is passed through the gate to the output If A is low, B’ is passed through the gate to the output

12. Pass Transistor At right, –(a) is a 2-input NAND pass transistor circuit –(b) is a 2-input NOR pass transistor circuit Each circuit requires 8 transistors, double that required using conventional CMOS realizations

13. Pass Transistor Pass-transistor logic gate can implement Boolean functions NOR, XOR, NAND, AND, and OR depending upon the P1- P4 inputs, as shown below. –P1,P2,P3,P4 = 0,0,0,1 gives F(A,B) = NOR –P1,P2,P3,P4 = 0,1,1,0 gives F(A,B) = XOR –P1,P2,P3,P4 = 0,1,1,1 gives F(A,B) = NAND –P1,P2,P3,P4 = 1,0,0,0 gives F(A,B) = AND –P1,P2,P3,P4 = 1,1,1,0 gives F(A,B) = OR Circuit can be operated with clocked P pull-up device or inverter- based latch

14. Transmission Gates N-Channel MOS Transistors pass a 0 better than a 1 P-Channel MOS Transistors pass a 1 better than a 0 This is the reason that N-Channel transistors are used in the pull-down network and P-Channel in the pull-up network of a CMOS gate. Otherwise the noise margin would be significantly reduced.

15. TRANSMISSION GATES  NMOS pass transistor passes a strong 0 and a weak 1.  PMOS pass transistor passes a strong 1 and a weak 0.  Combine the two to make a CMOS pass gate which will pass a strong 0 and a strong 1.

16. TRANSMISSION GATES  NMOS pass transistor passes a strong 0 and a weak 1.  PMOS pass transistor passes a strong 1 and a weak 0.  Combine the two to make a CMOS pass gate which will pass a strong 0 and a strong 1. Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well

17. TRANSMISSION GATE Problems with transmission gates  No isolation between the input and output.  Output progressively deteriorates as it passes through various stages. However designs get simplified.

18. Series Parallel Structures (3) G S D G S D N Switch P Switch 0 1 1 0 Passes “good zeros” Passes “good ones” Bi-directional Switch Open Circuit, High Z S S’

19. Transmission Gates A transmission gate is a essentially a switch that connects two points. In order to pass 0’s and 1’s equally well, a pair of transistors (one N-Channel and one P-Channel) are used as shown below: When s = 1 the two transistors conduct and connect x and y The top transistor passes x when it is 1 and the bottom transistor passes x when it is 0 When s = 0 the two transistor are cut off disconnecting x and y

20. Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well Four representations of CMOS Transmission Gate (TG)

21. Analysis of CMOS TG (1/4)

22. 22 Transmission Gates (Pass Gates) (1/2) –With body effect, for V DD = 5V, the value on V out can be around 3.0 to 3.5 V. This reduced level diminishes NM H and the current drive for the gate or gates driven by the pass transistor. –For both NMOS and CMOS, the lack of current drive slows circuit operation and NM H can be particularly problematic. As a consequence, in CMOS, a pFET is added to form a transmission gate. Transmission Gates –Symbols: A B C C A B C C Circuit Popular Usage

23. 23 Transmission Gates (2/2) –Operation C is logic high  Both transistors are turned on and provide a low-resistance current path between nodes A and B. C is logic low  Both transistors will be off, and the path between nodes A and B will be open circuit. This condition is called the high-impedance state. –With the parallel pFET added, it can transfer a full V DD from A to B (or B to A). It can also charge driven capacitance faster. –The substrates of NMOS and PMOS are connected to ground and V DD, respectively. Therefore, the substrate-bias effect must be taken into account.

24. Transmission Gate Circuits A CMOS TG is created by connecting an nFET and pFET in parallel –Bi-directional –Transmit the entire voltage range [0, V DD ] Figure Transmission gate (TG)

25. Transmission Gate Circuits Exercise

26. XOR gate

27. BAF 000 011 101 110

28. Logic Design using TG (2/3) TG based XOR/XNOR TG based OR gate (2.81)(2.82) (2.83) Figure 2.62 TG-based exclusive-OR and exclusive-NOR circuits (a) XOR circuit (b) XNOR circuit Figure 2.63 A TG-based OR gate

29. Logic Design using TG (3/3) Alternate XOR/XNOR Circuits –Mixing TGs and FETs which are designed for exclusive-OR and equivalence (XNOR) functions –It’s important in adders and error detection/correction algorithms Figure 2.64 An XNOR gate that used both TGs and FETs

30.  The 2:1 MUX can be modified to produced other useful function, such as XOR & XNOR circuits. T RANSMISSION G ATE a b b XOR a b XNOR s TG 0 F P0P0 P1P1 TG 1 s

31. Tristates Tristate buffer produces Z when not enabled ENAY 00Z 01Z 100 111

32. 32 Nonrestoring Tristate Transmission gate acts as tristate buffer –Only two transistors –But nonrestoring Noise on A is passed on to Y

33. Tristate Inverter Tristate inverter produces restored output –Violates conduction complement rule –Because we want a Z output

34. Complementary Pass-Transistor Logic (CPL) Utilizes CMOS transmission gate (or just the single polarity version of TG) to perform logic –Logical inputs may be applied to both the device gates as well as device source/drain regions –Only a limited number of Pass Gates may be ganged in series before a clocked Pull-up (or pull- down) stage is required (a) and (b) show simple XNOR implementation: –If A is high, B is passed through the gate to the output –If A is low, -B is passed through the gate to the output (c) shows XNOR circuit including a cross-coupled input with P pull-up devices which does not require inverted inputs R. W. Knepper SC571, page 5-23