1. 3. Logic Gate 3.1 Introduction static, fully complementary CMOS psudo-nMOS, domino logic 3.2 Combinational Logic Functions combinational logic ---- specification expression logic gate networks ---- implementation area, delay, power ---- costs

2. literal [Completeness] Function {|}=NAND function: complete 1:a|(a|a) = a|a’ = 1 0:{a|(a|a}|{a|(a|a)} = 1|1 = 0. a’:a|a = a’. ab:(a|b)|(a|b) = ab a+b:(a|a)|(b|b) = a’|b’=a+b NOR function: complete AND and OR function: not complete [Irredundant] no literal can be removed. redundant Ab+ab’=a

3. 3.3 Static Complementary Gates 3.3.1 Gate Structure Pullup network (pMOS) output is connected to VDD Pulldown network (nMOS) Output is connected to VSS VDD VSS

4. Pullup network (pMOS) output is connected to VDD when ab=0. Pulldown network (nMOS) Output is connected to VSS when ab=1. VDD VSS CMOS NAND

5. Pullup network (pMOS) output is connected to VDD when a+b=0. Pulldown network (nMOS) Output is connected to VSS when a+b=1. VDD VSS CMOS NOR

6. Static Complementary gate [a(b+c)]’ Dual graph

7. And Or Inverter (AOI) gate (ab+c)’

8. 3.3.2 Basic Gate Layouts Layout of Inverter

9. Layout of NAND gate

10. Layout of NOR gate

11. Layout of a wide transistor by split into two sections.

12. 3.3.3 Logic Levels VOH: minimum voltage output for logic 1. VOL: maximum voltage output for logic 0. VIH: minimum voltage input for logic 1. VIL: maximum voltage input for logic 0. VOL < VIL VOH > VIH

13. Minimum size transistors VIL VIH VOL VOH Noise Margin NML = VIL-VOL NMH = VOH-VIH

14. 3.3.4 Delay

20. 3.3.5 Power Consumption

21. Speed-power product = power-delay product SP=(1/f)P=CV 2 3.3.6 The Speed-Power Product

22. 3.3.7 Layout and Parasitics Resistance parastics

23. 3.3.8 Driving Large Loads Alpha=(Cbig/Cg)(1/n) Ttot = Nopt=

24. Delta1=r1 x (C1+---+Cn) =n rc Delta2=r2 x (C2+----+Cn) =(n-1)rc DeltaN=rn x Cn =rc total=Delta1+ ----- + DeltaN =n(n+1)/2 x rc 3.4 Wires and Delay 3.4.1 Elmore Delay Model

25. 3.4.2 Wire Sizing Optimum-shaped wire

26. 3.4.3 RC Trees

27. 3.5 Switch Logic Logic 0 transfer Logic 1 transfer

28. 3.6 Alternative Gate Cirucits 3.6.1 Pseudo-nMOS Logic

30. 3.6.2 DCVS (Differential Cascaded voltages switch logic) Logic

32. 3.6.3 Domino Logic

33. Successive evaluation in a domino logic network

36. Charge sharing