1. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 1 Chapter 6 Introduction to Digital Electronics Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock Modified by Ming Ouhyoung

2. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 2 Chapter Goals Introduce binary digital logic concepts Explore the voltage transfer characteristics of ideal and nonideal inverters Define logic levels and logic states of logic gates Introduce the concept of noise margin Present measures of dynamic performance of logic devices Review of Boolean algebra Investigate simple transistor implementations of the inverter and other logic circuits Explore basic design techniques of logic circuits

3. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 3 Brief History of Digital Electronics Digital electronics can be found in many applications in the form of microprocessors, microcontrollers, PCs, DSPs, and an uncountable number of other systems. The design of digital circuits has progressed from resistor- transistor logic (RTL) and diode-transistor logic (DTL) to transistor-transistor logic (TTL) and emitter-coupled logic (ECL) to NMOS and now Complementary MOS (CMOS) The density and number of transistors in microprocessors has increased from 2300 in the 1971 4-bit 4004 microprocessor to 25 million in the more recent IA-64 chip, chips employing more than 1 B transistors have been introduced and it is projected to reach over 10 billion transistors by 2018.

4. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 4 Ideal Logic Gates Binary logic gates are the most common style of digital logic The output will consist of either a 0 (low) or a 1 (high) –(Positive Logic Convention) The most basic digital building block is the inverter

5. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 5 The Ideal Inverter The ideal inverter has the following voltage transfer characteristic (VTC) and is described by the following symbol V + and V - are the supply rails, and V H and V L describe the high and low logic levels at the output

6. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 6 Logic Level Definitions An inverter operating with power supplies at V + and 0 V can be implemented using a switch with a resistive load

7. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 7 Logic Voltage Level Definitions V L – The nominal voltage corresponding to a low-logic state at the output of a logic gate for v i = V H V H – The nominal voltage corresponding to a high-logic state at the output of a logic gate for v i = V L V IL – The maximum input voltage that will be recognized as a low input logic level V IH – The minimum input voltage that will be recognized as a high input logic level V OH – The output voltage corresponding to an input voltage of V IL V OL – The output voltage corresponding to an input voltage of V IH

8. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 8 Logic Voltage Level Definitions (cont.) Note that for the voltage transfer characteristic (VTC) of the nonideal inverter, there is now an undefined logic state.

9. CMOS FET/Transistor 速度如何決定 ? 台積電 (TSMC) 如何從製程中得到營業利益 ? 如何超越別的競爭 ? IC (CMOS FET) 速度如何加快 ? 製程 Scaling 如何影響 ? 速度, 熱量, 晶片密度 如何與製程 Scaling ( alpha factor) 產生關聯 ? Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 9

10. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 10 Noise Margins Noise margins represent “safety margins” that prevent the circuit from producing erroneous outputs in the presence of noisy inputs Noise margins are defined for low and high input levels using the following equations: one’s output is the input of next stage NM L = V IL – V OL NM H = V OH – V IH

11. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 11 Noise Margins (cont.) Graphical representation of where noise margins are defined

12. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 12 Logic Gate Design Goals An ideal logic gate is highly nonlinear and attempts to quantize the input signal to two discrete states. In an actual gate, the designer should attempt to minimize the undefined input region while maximizing noise margins The input should produce a well-defined output, and changes at the output should have no effect on the input Voltage levels at the output of one gate should be compatible with the input levels of a following gate The gate should have sufficient fan-out and fan-in capabilities The gate should consume minimal power (and area for ICs) and still operate under the design specifications

13. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 13 Dynamic Response of Logic Gates An important figure of merit to describe logic gates is the response in the time domain The rise and fall times, t f and t r, are measured at the 10% and 90% points on the transitions between the two states as shown by the following expressions: V 10% = V L + 0.1  V V 90% = V L + 0.9  V = V H – 0.1  V where  V is the logic swing given by  V = V H - V L

14. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 14 Propagation Delay Propagation delay describes the amount of time between a the input reaching the 50% point and the output reaching the 50% point. The 50% point is described by the following: The high-to-low propagation delay,  PHL, and the low-to- high propagation delay,  PLH, are usually not equal, but can be combined as an average value:

15. Circuit Delay– RC circuit Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 15

16. Delay calculation What is the charge of a capacitor C when applied a voltage of V? Answer: Q = C*V When a capacitor is connected with a resistor R, and initial voltage of capacitor is V, what will be the voltage vs time plot? dQ(t)/dt = current = I(t), I(t)*R = Vr, Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 16

17. Homework #2 4.2, 4.15, 4.37, 4.79, 4.80 Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 17

18. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 18

19. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 19 Dynamic Response of Logic Gates

20. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 20 Power Delay Product The power-delay product (PDP) is used as a metric to describe the amount of energy (Joules) required to perform a basic logic operation and is given by the following equation where P is the average power dissipated by the logic gate:

21. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 21 Review of Boolean Algebra (11/7) AZ 01 10 ABZ 000 011 101 111 ABZ 000 010 100 111 NOT Truth Table OR Truth Table AND Truth Table ABZ 001 010 100 110 ABZ 001 011 101 110 NOR Truth Table NAND Truth Table

22. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 22 Logic Gate Symbols and Boolean Expressions

23. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 23 NMOS Logic Design MOS transistors (both PMOS and NMOS) can be combined with resistive loads to create single channel logic gates The circuit designer is limited to altering circuit topology and the width-to-length (W/L) ratio since the other factors are dependent upon processing parameters

24. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 24 NMOS Inverter with a Resistive Load The resistor R is used to “pull” the output high M S is the switching transistor used to “pull” the output low The size of R and the W/L ratio of M S are the design factors that need to be chosen

25. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 25 Load Line Visualization The operation of the NMOS output (i D, v DS ) characteristics. Load line equation:

26. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 26 NMOS with Resistive Load Design Example Design a NMOS resistive load inverter for –V DD = 3.3 V –P = 0.1 mW when V L = 0.2 V –K n = 60  A/V 2 –V TN = 0.75 V Find the value of the load resistor R and the W/L ratio of the switching transistor M S

27. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 27 Example continued First the value of the current through the resistor (for v O = V L ) must be determined by using the following: The value of the resistor can now be found by the following which assumes that the transistor is on and the output is low:

28. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 28 Example Continued For v I = V H = 3.3 V, and v O = V L = 0.2V, the transistor’s drain-source voltage V DS will be less than V GS -V TN. Therefore it will be operating in the triode region. Using the triode region equation for the MOSFET, the W/L ratio can be found:

29. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 29 On-Resistance of the Switching Device, M S The NMOS resistive load inverter can be thought of as a resistive divider when the output is low, described by the following expression:

30. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 30 On-Resistance of M S (cont.) When the NMOS resistive load inverter’s output is low, the On-Resistance R on of the NMOS can be calculated with the following expression: Note that R on should be kept small compared to R to ensure that V L remains low, and also that its value is nonlinear, since it has a dependence on v DS

31. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 31 Load Resistor Problems For completely integrated circuits, R must be implemented on chip using the shown structure Using the given equation, it can be seen that resistors take up a large area of silicon as in an example 95k  resistor

32. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 32 Using Transistors in Place of a Resistor NMOS load with a)gate connected to the source b)gate connected to ground c)gate connected to V DD d)gate biased to linear region e)a depletion-mode NMOSFET f)gate grounded PMOS load Note that a) and b) are not useful. (M L always off.)

33. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 33 Static Design of the NMOS Saturated Load Inverter Schematic for a NMOS saturated load inverter Cross-section for a NMOS saturated load inverter

34. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 34 NMOS Saturated Load Inverter Design Strategy Given V DD, V L, and the power level, find I DD from V DD and power Assume M S off, and find high output voltage level V H Use the value of V H for the gate voltage of M S and calculate (W/L) S of the switching transistor based on the design values of I DD and V L Find (W/L) L (load transistor) based on I DD and V L Check the operating region assumptions of M S and M L for v o = V L Verify design with a SPICE simulations

35. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 35 NMOS Saturated Load Inverter Design Example Design an saturated load inverter given the following specifications:

36. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 36 NMOS Saturated Load Inverter Design Example First find V H (The output cannot exceed the positive power supply voltage.)

37. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 37 NMOS Saturated Load Inverter Design Example (11/14) For v o = V L, M S is on (in the triode region), and M L is in saturation. Find the W/L ratios of the two transistors

38. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 38 NMOS Inverter Summary Resistive load inverter takes up too much area for and IC design. The saturated load configuration is the simplest design, but V H never reaches V DD, and it has a slow switching speed. The linear load inverter fixes the speed and logic level issues, but it requires an additional power supply for the load gate. The depletion-mode NMOS load requires the most processing steps, but needs small area to achieve the high speed, V H = V DD, and best combination of noise margins. The Pseudo NMOS inverter offers the best speed with the lowest area.

39. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 39 Typical Inverter Characteristics Inverter w/ Resistor Load Saturated Load Inverter Linear Load Inverter Inverter w/ Depletion- Mode Load Pseudo- NMOS Inverter V H (V)2.501.552.50 V L (V)0.20 N ML (V)0.25 0.120.430.46 N MH (V)0.960.330.960.900.75 Relative Area 28806.397.944.033.33

40. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 40 Reference Inverter Designs for Later Sections

41. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 41 NOR Gates Simplified switch model for the NOR gate with M A on Two-input NOR gate

42. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 42 NAND Gates Simplified switch model for the NOR gate with A and B on (right) Two-input NAND gate (left)

43. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 43 NAND Gate Device Size Selection The NAND switching transistors can be sized based on the depletion-mode load inverter To keep the low voltage level comparable with the inverter, the desired R on of M A and M B must be 0.5R on of M S,Inverter This can be accomplished by approximately doubling (W/L) A and (W/L) B The sizes can also be chosen by using the design value of V L and using the following equation:

44. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 44 NAND Gate Device Size Selection (cont.) Two sources of error that arise are the facts that the V SB ’s and V GS ’s of the two transistors are not equal. These factors should be considered for proper gate design The technique used to calculate the size of the load transistor for the NAND gate is exactly the same as for the depletion-load inverter

45. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 45 Layout of the NMOS Depletion-Mode NOR and NAND Gates

46. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 46 6.9 Complex NMOS Logic Design An advantage of NMOS technology is that it is simple to design complex logic functions based on the NOR and NAND gates The circuit in the figure has the logic function: Y = A + BC + BD

47. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 47

48. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 48

49. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 49 Complex Logic Gate Transistor Sizing There are two ways to find the W/L ratios of the switching transistors 1)Use the worst-case path (most devices in series) and choose the W/L ratios to achieve the value of R on equivalent to that of the inverter 2)Partitioning the circuit into a series sub-networks, and make the equivalent on-resistances equal

50. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 50 Complex Logic Gate Transistor Sizing The figure on the left shows the worst case technique to find the sizes where (W/L) S = 2.06 is the reference inverter ratio for this technology and the longest path is 3 transistors are in series The figure on the right shows the partitioning technique to find the sizes which gives two 4.12/1 ratios in series which is 2(2.06/1)

51. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 51 Static Power Dissipation Static Power Dissipation is the average power dissipation of the logic gate for the high and low logic states: I DDH = current in the circuit for v O = V H I DDL = current in the circuit for v O = V L Since I DDH = 0 A for v O = V H :

52. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 52 Dynamic Power Dissipation Dynamic Power Dissipation is the power dissipated during the process of charging and discharging the load capacitance connected to the logic gate Discharging Charging

53. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 53 Dynamic Power Dissipation Based on the energy equation, the energy delivered to the capacitor can be found by: The energy stored by the capacitor is: The energy lost in the resistive elements is given by:

54. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 54 Dynamic Power Dissipation The total energy lost in the first charging and discharging of the capacitor through resistive elements is given by: Thus, if the logic circuit is switching at a frequency f, the dynamic power dissipation is given by:

55. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 55 Power Scaling in MOS Logic By reducing the W/L of the load and switching transistors of an inverter, it is possible to reduce the power dissipation by the same factor without sacrificing V H and V L. This same concept works for increasing the power which will increase the dynamic response.

56. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 56 Power Scaling in MOS Logic a)Original Saturated Load Inverter b)Saturated Load inverter designed to operate at 1/3 the power c)Original Depletion-Mode Inverter d)Depletion-mode inverter designed to operate at twice the power

57. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 57 Dynamic Behavior Capacitance in MOS Logic Circuits The MOS device has capacitances C SB, C GS, C DB, and C GD that need to be considered for dynamic response analysis, but depending on the configuration, some of them will be shorted. The capacitances seen at a node can be lumped together.

58. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 58 Fan-out Limitations DC loading constraints are not usually important for MOS logic circuits since they normally drive capacitive loads (i.e. the gate of a MOS) As the number of gates the output (fan-out) of a logic device has to drive, the load capacitance increases, and the time response degrades This notion implies that the fan-out that a logic circuit can drive will be limited to time delay tolerances of the circuit

59. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 59 Dynamic Response of the NMOS Inverter with a Resistive Load Rise time is defined as the time for the output to change from 10% to 90% of the complete transition.

60. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 60 Dynamic Response of the NMOS Inverter with a Resistive Load Delay time is defined as the time required for the output to change 50%. Using a similar analysis we get the following results for rise/fall times and propagation delay: where R and C are the resistance and capacitance seen at the output. For low-to-high transitions, R is the load resistance (M S is off). For high-to-low transitions, the on resistance of M S, R onS, varies during the transition but an effective R, R eff, can be approximated as 1.7 R onS from SPICE simulation.

61. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 61 Pseudo NMOS Inverter - Dynamic Response

62. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 62 Pseudo NMOS Inverter - Dynamic Response Example Find t f, t r,  PHL,  PLH for a pseudo NMOS inverter where: –(W/L) S = 2.22/1 and (W/L) L = 1.11/1 –C LOAD = 1 pF –V TN = 0.6 V and V TP = -0.6 V –V DD = 2.5 V –K n = (2.06)(100  10 -6 A/V 2 ) –K L = (1.11)(40  10 -6 A/V 2 )

63. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 63 Pseudo NMOS Inverter - Dynamic Response Example First find the on-resistances of the two switch and load devices

64. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 64 NMOS Inverter with a Depletion-Mode Load - Dynamic Response Example Now calculate delays from the R eff approximations: SPICE simulations show good agreement and result in values of 3 ns, 7 ns, 15.0 ns, and 35.0 ns.

65. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 65 Comparison of Load Devices The current has been normalized to 80  A for v o = V OL = 0.20 V in the figure for the various types of inverters

66. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 66 Comparison of Load Devices The saturated load devices have the poorest fall time since they have the lowest load current delivery The saturated load devices also reach zero current before the output reaches 2.5 V The linear load device is faster than the saturated load device, but about equal to the resistive load speed. The fastest  PLH is for the pseudo NMOS device as a result of the PMOS device

67. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 67 Gate Device Geometry Scaling based Upon Reference Circuit Simulation State-of-the-art short gate length technologies are hard to analyze Scaling can be used to properly set W/L for a given load capacitance relative to reference gate simulation with a reference load. Scaling allows us to calculate a new geometry (W/L)' in terms of a target load and delay.

68. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 68 Pseudo NMOS Propagation Delay - Design Example Design a pseudo NMOS inverter with a propagation delay (  P ) of 2 ns when driving a capacitance of 5 pF, and find (W/L) S, (W/L) L, t f, and t r for: –C LOAD = 5 pF –V TN = 0.6 V and V TP = -0.6 V –V DD = 2.5 V, V H = 2.5 V and V L = 0.20 V –Base on a reference inverter with: (W/L) S = 2.22/1 (W/L) L = 1.11/1 –Use equations from Table 6.10

69. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 69 Propagation Delay - Design Example

70. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 70 Propagation Delay Design Example - SPICE Simulation The simulated transition times were 0.75 ns and 3.5 ns, yielding a propogation delay of 2.1 ns. The rise and fall times were 8.0 ns and 1.8 ns.

71. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 71 PMOS Logic PMOS logic circuits predated NMOS logic circuit, but were replaced since they operate at slower speeds Resistive LoadSaturated LoadLinear LoadDepletion-Mode Load Pseudo PMOS

72. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 72 PMOS NAND and NOR Gates NOR GateNAND Gate

73. Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 73 End of Chapter 6

74. HW6 6.28 6.109 6.117 Microelectronic Circuit Design, 4E McGraw-Hill Chap 6 - 74