1. Processor: Datapath and Control
Chapter 5

2. Components of a Computer
Processor
Control
Datapath
Memory
Devices
Input
Output

3. Code Stored in Memory Memory Processor Devices Control Input Datapath
Control
Input
Datapath
Output
2. These data are kept in the computer’s memory until ...
Note that memory holds both INSTRUCTIONS and DATA and you can’t tell the difference. They are both just 32 bit strings of zeros and ones.

4. Processor Fetches an Instruction
Processor fetches an instruction from memory
Memory
Processor
Devices
Control
Input
Datapath
Output
3. The processor request and process them.

5. Control Decodes the Instruction
Control decodes the instruction to determine what to execute
Processor
Devices
Control
Memory
Input
Datapath
Output
3. The processor control decodes the instruction in order to figure out what to tell the datapath to do

6. Datapath Executes the Instruction
Datapath executes the instruction as directed by control
Processor
Devices
Control
Memory
Input
Datapath
contents Reg #4 ADD contents Reg #2
results put in Reg #2
Output
4. The operation of the datapath is controlled by the processor’s controller.

7. What Happens Next? Memory Processor Devices Control Input Datapath
Control
Input
Datapath
Output
For lecture
3. What happens next (next instruction is fetched/how to tell where that instruction is located in memory/…)
Fetch
Exec
Decode

8. Output Data Stored in Memory
At program completion the data to be output resides in memory
Memory
Processor
Devices
Control
Input
Datapath
Output
5. The data to be output are kept in the computer’s memory until ...

9. Processor
Two main components
Datapath
Control

10. Design of Processor Analyze the instruction set architecture
Select the datapath elements each instruction needs
Assemble the datapath
determine the controls required
Assemble the control logic

11. A Basic MIPS Implementation
will implement the following subset of MIPS core instructions
lw, sw
add, sub, and, or, slt
beq, j

12. Steps in executing add instruction
add $t0, $t1, $t2
Send PC to memory that contains the code and fetch instruction
PC = PC+4
Read $t1 and $t2 from register file
Perform $t1 + $t2
Store result in $t0

13. Steps in executing lw instruction
lw $t0, offset($t1)
Send PC to memory that contains the code and fetch instruction
PC = PC+4
Read $t1 from register file
Perform $t1 + sign-extend(offset)
Read value at Mem[$t1 + sign-extend(offset)]
Store result in $t0

14. Steps in executing beq instruction
beq $t0, $t1, Label
Send PC to memory that contains the code and fetch instruction
PC = PC+4
Read $t0 and $t1 from register file
Perform $t0 - $t1
If result = 0, set PC=Label

15. Steps in implementing these instructions
Common steps
Send PC to memory that contains the code and fetch the instruction
Set PC = PC+4
Read one or two registers
Steps dependent on instruction class
Use ALU
Arithmetic/logical instr for operation execution
lw/sw for address calculation
beq for comparison
Update memory or registers
lw/sw read or write to memory
Arithmetic/logical instr write to register
beq updates PC

16. Components needed for Fetching and Incrementing PC

17. Datapath for Fetching and Incrementing PC

18. Components needed for R-format Instructions
add $t0, $t1, $t2: $t0= $t1 + $t2
and $t0, $t1, $t2: $t0= $t1 AND $t2

19. Register File
Consists of a set of 32 registers that can be read and written
Registers built from D flip-flops
has two read ports and one write port
Register number are 5 bit long
To write, you need three inputs:
a register number, the data to write, and a clock (not shown explicitly) that controls the writing into the register
The register content will change on rising clock edge 5 5 5
Write signal must be asserted to write the data to register on rising edge
Register numbers are 5 bits
What happens if the same register is read and written during a clock cycle? Because the write of the register file occurs on the clock edge, the register will be valid during the time it is read, The value returned will be the value written in an earlier clock cycle

20. Portion of datapath for R-format instruction4 rs rt rd
31-26
25-21
20-16
15-11
10-6
5-0
opcode rs rt rd
shamt
funct
R-format

21. Components needed for load and store instructions
lw $t0, offset($t1): $t0=Mem[$t1 + se(offset)]
sw $t0, offset($t1): Mem[$t1 + se(offset)]=$t0

22. Memory Unit MemRead to be asserted to read
MemWrite to be asserted to write
Both MemRead and MemWrite not to be asserted in same clock cycle
Memory is edge triggered for writes
Address
ReadData
Write Data
MemWrite

23. Load/Store instruction datapath
lw $t0, offset($t1): $t0=Mem[$t1 + se(offset)]
sw $t0, offset($t1): Mem[$t1 + se(offset)]=$t0 4
31-26
25-21
20-16
15-0
opcode rs rt
offset
I-format

24. Load instruction datapath
lw $t0, offset($t1): $t0=Mem[$t1 + se(offset)] 4 rs rt
offset
31-26
25-21
20-16
15-0
opcode rs rt
offset
I-format

25. Store instruction datapath
sw $t0, offset($t1): Mem[$t1 + se(offset)]=$t0 4 rs rt
offset
31-26
25-21
20-16
15-0
opcode rs rt
offset
I-format

26. Branch Instruction Datapathrs rt
31-26
25-21
20-16
15-0
opcode rs rt C C
If ($rs-$rt)=0, PC=PC+4+(C.4)

27. Creating a single Datapath
Simplest Design: Single Cycle Implementation
Any instruction takes one clock cycle to execute
This means no datapath elements can be used more than once per instruction
But datapath elements can be shared by different instruction flows

28. 4 4

29. Composite Datapath for R-format and load/store instructions

30. Composite Datapath for R-format and load/store instructions4 + P C
Instruction Memory

31. Composite datapath for R-format, load/store, and branch instructions

32. Datapath for for R-format, load/store, and branch instructions
ALU Operation 4

33. R-format 1 0000(and) 0001(or) 0010(add) 0110(sub) lw 0010 (add) sw X
Instruction
RegDst
RegWrite
ALUSrc
MemRead
MemWrite
MemToReg
PCSrc
ALU operation
R-format 1
0000(and)
0001(or)
0010(add)
0110(sub) lw
0010 (add) sw X
beq x
1 or 0
0110 (sub)

34. Control We next add the control unit that generates
write signal for each state element
control signals for each multiplexer
ALU control signal
Input to control unit: instruction opcode and function code

35. Control Unit Divided into two parts Main Control Unit ALU Control Unit
Input: 6-bit opcode
Output: all control signals for Muxes, RegWrite, MemRead, MemWrite and a 2-bit ALUOp signal
ALU Control Unit
Input: 2-bit ALUOp signal generated from Main Control Unit and 6-bit instruction function code
Output: 4-bit ALU control signal

37. Truth Table for Main Control Unit

38. Main Control Unit

39. ALU Control Unit
Must describe hardware to compute 4-bit ALU control input given
2-bit ALUOp signal from Main Control Unit
function code for arithmetic
Describe it using a truth table (can turn into gates):

40. ALU Control bits
0010
0110
0000
0001
0111

41. ALU Control Unit