1. Computer Organization and Design Lecture 16 – Combinational Logic Blocks Close call!   Cal squeaked by Washington in Overtime 31-24. We win, and then we drop a spot in the polls. Yikes! UCLA soon. calbears.cstv.com

2. Review Use this table and techniques we learned to transform from 1 to another

3. Today Data Multiplexors Arithmetic and Logic Unit Adder/Subtractor

4. Data Multiplexor (here 2-to-1, n-bit-wide) “mux”

5. N 个 1-bit-wide mux How many rows in TT?

6. 如何构建 1-bit-wide mux?

7. 4-to-1 Multiplexor? 真值表中有多少行 ?

8. 其它方式完成 ? Ans: 层次结构 !

9. 算术逻辑单元 Arithmetic and Logic Unit 大多数处理器都包含一个称为算术逻辑单元的逻 辑块 “Arithmetic and Logic Unit” (ALU) 下面将讲授进行加 (ADD), 减 (SUB), 按位与 (AND), 按位或 (bitwise OR)

10. Our simple ALU

11. 加 / 减法设计 – 如何进行 ? 真值表, 然后确定与或范式, 然后简化 将问题分解为更小的问题，使用层次方法或者连接 的方法进行求解

12. Adder/Subtracter – One-bit adder LSB…

13. Adder/Subtracter – One-bit adder (1/2)…

14. Adder/Subtracter – One-bit adder (2/2)…

15. N 1-bit adders  1 N-bit adder 关于溢出 ? Overflow = c n ? 无符号数是这样的 +++ b0b0

16. What about overflow? 表示 : 数 正数 反 补 -2 10 01 10 -1 01 10 11 0 00 1 01

17. 关于溢出 (overflow)? 考虑二位有符号数加法及溢出 & overflow: 10 = -2 + -2 or -1 11 = -1 + -2 only 00 = 0 NOTHING! 01 = 1 + 1 only Highest adder C 1 = Carry-in = C in, C 2 = Carry-out = C out 10 10 01 10 10 01 01 11 11 00 10 11 01 00 01 00 11 11 00 00 10 10 01 00 00 00 11 11 00 00 C in but no C out C out but no C in ± # What op?

18. What about overflow? Consider a 2-bit signed # & overflow: 10 = -2 + -2 or -1 11 = -1 + -2 only 00 = 0 NOTHING! 01 = 1 + 1 only Overflows when… C in, but no C out  A,B both > 0, overflow! C out, but no C in  A,B both < 0, overflow! ± #

19. Overflow detection? Another explain 当 a,b 不同号时，不会溢出 两个正数相加 在最高位不可能有进位 在次高位有进位，则加成了负数 两个负数相加 在最高位总有进位 如果次高位无进位，则加成了负数 无论何种情况，只要两个进行不同则发生溢出

20. Extremely Clever Subtractor A - B = A + (-B) = A + ~B +1 1 xor b =~b 0 xor b = b

21. Peer Instruction A. Truth table for mux with 4-bits of signals has 2 4 rows B. We could cascade N 1-bit shifters to make 1 N-bit shifter for sll, srl C. If 1-bit adder delay is T, the N-bit adder delay would also be T ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT

22. Peer Instruction Answer A. Truth table for mux with 4-bits of signals is 2 4 rows long B. We could cascade N 1-bit shifters to make 1 N-bit shifter for sll, srl C. If 1-bit adder delay is T, the N-bit adder delay would also be T ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT A. Truth table for mux with 4-bits of signals controls 16 inputs, for a total of 20 inputs, so truth table is 2 20 rows…FALSE B. We could cascade N 1-bit shifters to make 1 N-bit shifter for sll, srl … TRUE C. What about the cascading carry? FALSE

23. “And In conclusion…” Use muxes to select among input S input bits selects 2S inputs Each input can be n-bits wide, indep of S Implement muxes hierarchically ALU can be implemented using a mux Coupled with basic block elements N-bit adder-subtractor done using N 1- bit adders with XOR gates on input XOR serves as conditional inverter

24. Intro to hardware description language

25. Verilog Hardware Description Language

26. Very Brief Verilog Introduction

27. Verilog Example : 4-input multiplexor

28. Verilog Example : Accumulator

29. Last word (for now) on Verilog

30. Verilog and Boolean Equations Besides the two major styles, structural and behavioral, a third style (somewhat in between) called dataflow Continuous Assignment statements // y = ab + ac + bc; wire a, b, c, y; assign y = a & b | a & c | b & c; Not like a normal assignment in programming languages. This assign happens continuously. Whenever anything on the RHS changes, the LHS is updated.

31. Verilog Continuous Assign The Boolean operators are defined to be bitwise: // Y = AB; wire A[3:0], B[3:0]; assign Y = A & B; // Or equivalently assign Y[0] = A[0] & B[0]; assign Y[1] = A[1] & B[1]; assign Y[2] = A[2] & B[2]; assign Y[3] = A[3] & B[3];

32. Verilog Bitwise Operators

33. Concatenation in Verilog wire A[7:0], B[7:0]; wire C[3:0], D[11:0]; wire Y[15:0]; assign Y = { A, B }; // Makes a longer bit vector from A with B Concatenation on the LHS assign { C, D } = Y; // Splits up Y into pieces assign { C, D } = { A, B }; // Also works assign {OPCODE, RS, RT, IMMED} = INSTRUCTION; // Might be useful

34. Replication n{m} Replicates m n-times. Example: wire X[31:0]; wire IMMED[15:0]; assign X = { 16{IMMED[15]}, IMMED}; // Sign-extends IMMEDIATE into X Concatenation, replication operations don’t generate any combinational logic, then only generate wires.

35. Conditional Operator