1. DIGITAL 2 : EKT 221 Date : 15 th July 2005 Lecture : 1 hrs

2. Reminder Mini Project – group of 4 persons from the same program Dateline for group formation – Next week Friday (22/7/2005) Dateline for project title, synopsis @ paperwork submission (20/8/2005) Project samples – to give as handouts Project requirements – to give as handouts

3. Mini Project Marking Scheme Presentation (50 marks)  Project explaination (comprehensiveness) - 20  Attitude & Attire -10  Team Coordination - 10  Add-ons (Project Details) - 10 Posters, Flowcharts

4. Mini Project Marking Scheme Creativity (30 marks)  Digital Design Development – 15 Complexity of Design Originality  Hardware Skills - 15 Additional Circuit Development Order of Development (Systematic, tidiness and orderly)

5. Mini Project Marking Scheme Jury Evaluation (10 marks)  Communication level among group members  Contribution level among group members Peer Evaluation (10 marks)  Based on group members’ evaluation

6. Combinational Arithmetic Circuits Addition:  Half Adder (HA).  Full Adder (FA).  Carry Ripple Adders. Subtraction:  Half Subtractor.  Full Subtractor.  Borrow Ripple Subtractors.  Subtraction using adders.

7. Half Adder X0011X0011 Y0101Y0101 S0110S0110 C-out 0 1 Half Adder Truth Table: Inputs Outputs S = X  Y C-out = XY XYXY Sum S C-out Half Adder X Y S C-OUT

8. Full Adder X00001111X00001111 Y00110011Y00110011 S01101001S01101001 C-out 0 1 0 1 C-in 0 1 0 1 0 1 0 1 Full Adder Truth Table S(X,Y, C-in) =  (1,2,4,7) C-out(x, y, C-in) =  (3,5,6,7) Inputs Outputs S = X  Y  (C-in) C-out = XY + X(C-in) + Y(C-in) Full Adder XY S C-in C-out

9. Full Adder X1Y1 S1 C-in C-out Full Adder X0Y0 S0 C-in C-out C0 =0 Full Adder X2Y2 S2 C-in C-out Full Adder X3Y3 S3 C-in C-out C1 C2C3 C4 Data inputs to be added Sum output 4-bit Carry Ripple Adder 4-bit Adder X3X2X1X0 S3 S2 S1 S0 C-in C-out C4 Y3Y2Y1Y0 C0 =0 Inputs to be added Sum Output

10. 4-bit Subtractor Using 4-bit Adder 4-bit Adder X3 X2 X1 X0 D3 D2 D1 D0 C-in C-out C4 Y3 Y2 Y1 Y0 C0 = 1 Inputs to be subtracted Difference Output S3 S2 S1 S0

11. Encoder Encoder converts information such as decimal number or an alphabetical character into some binary coded form Example: 8-to-3 Binary Encoder

12. Decoder Example: 3 to 8 Binary Decoder

13. Decoder Example: Seven Segment Decoder A seven segment decoder has 4-bit BCD input and the seven segment display code as its output: In minimizing the circuits for the segment outputs all non-decimal input combinations (1010, 1011, 1100,1101, 1110, 1111) are taken as don’t-cares /Bl D C B A a b c d e f g 0 x x x x 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 1 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 -- don’t care inputs --

14. Multiplexer A 4 input multiplexer

15. Demultiplexer Example: 1- to -4 Demultiplexer

16. Latches:  S-R Latch  Gate S-R Latch  Gate D-Latch Flip-Flops:  Edge-Triggered Flip-Flop (S-R, J-K, D)  Asynchronous Inputs  Master-Slave Flip-Flop  Flip-Flop Operating Characteristics  Flip-Flop Applications  One-shots & The 555 Timer Latches & Flip Flop

17. Truth Table for each FF +ve / -ve edge triggered Waveform

18. JKFF Transition Table JKQtif QtQt + 1 00n.c 0 1 010 0 1 101 0 1 11T 0 1 Derive the from this equation to get JKFF Transition Table

19. JKFF Transition Table QtQt+1JK 000x 011x 10x1 11x0 Note : This Transition Table will be useful in your LAB 4 : Sequential Up/Down Binary Counter

20. Basic shift register function Serial in / serial out shift registers Serial in / parallel out shift registers Parallel in / serial out shift registers Parallel in / parallel out shift registers Bidirectional shift registers Shift register applications Shift Register

21. Serial In, Serial Out Shift Register (SISO)

22. Serial In, Parallel Out Shift register (SIPO) Data bits entered serially (right-most bit first) Difference from SISO is the way data bits are taken out of the register – in parallel. Output of each stage is available

23. Parallel In, Parallel Out Shift Register (PIPO) Immediately following simultaneous entry of all data bits,it appear on parallel output.

24. ASYNCHRONOUS COUNTER: A 2-bit asynchronous binary counter. Don’t have fixed time relationship with each other. Don’t occur at the same time. Don’t have a common clock pulse

25. SYNCHRONOUS COUNTER OPERATION A 2-bit synchronous binary counter.

26. UP/DOWN SYNCHRONOUS COUNTER A basic 3-bit up/down synchronous counter.

27. Reminder Your “Digital Fundamental” book is still essential for basic reference to this course. Do NOT sell it yet !!

28. THANK YOU