1. Chapter 9 Memory Organization By Jack Chung

2. MEMORY? RAM?

3. Hierarchy of Memory System  A computer system is not constructed using a single type of memory.  In fact, several types of memory are used.  Level 1 cache (L1 cache)  Level 2 cache (L2 cache)  Physical Memory(RAM)  Virtual Memory

4. How Virtual memory works? Virtual memory is a common part of most operating systems on desktop computers. It has become so common because it provides a big benefit for users at a very low cost.operating systemsdesktop computers

5. For example, if you load the operating system, and e-mail programs, a Web browser and 3D Computer Game into RAM simultaneously, 64 megabytes is not enough to hold it all. If there were no such thing as virtual memory, then once you filled up the available RAM your computer would have to say,

6. "Sorry, you can not load any more applications. Please close another application to load a new one!!!"

7. With virtual memory, what the computer can do is look at RAM for areas that have not been used recently and copy them onto the hard disk. This frees up space in RAM to load the new application.hard disk RAM Virtual Memory Disk Storage

8. The area of the hard disk that stores the RAM image is called a page file. It holds pages of RAM on the hard disk, and the operating system moves data back and forth between the page file and RAM. RAM Virtual Memory Disk Storage

9. When the microprocessor accesses the RAM, it does it in about 60 nanoseconds (60 billionths of a second). That's pretty fast, but it is much slower than the typical microprocessor. Microprocessors can have cycle times as short as 2 nanoseconds, so to a microprocessor 60 nanoseconds seems like an eternity.microprocessor RAM

10. What if we build a special memory bank, small but very fast (around 30 nanoseconds)? That's already two times faster than the main memory access. That's called a level 2 cache or an L2 cache.

11.  Level 2 cache (L2 cache) is usually outside of the microprocessor. L2 cache L2 cache Physical memory Physical memory Virtual memory storage Virtual memory storage Generic Memory Hierarchy

12. However there is an even smaller but faster memory system directly into the microprocessor's chip. That's an Level 1 cache, L1 cache is about 3.5 times faster than the L2 cache

13. Generic Memory Hierarchy  Level 1 cache (L1 cache) is incorporated directly into the microprocessor. Fastest Level L1 cache L1 cache L2 cache L2 cache Physical memory Physical memory Virtual memory storage Virtual memory storage CPU

14. Important facts about caching Cache technology is the use of a faster but smaller memory type to accelerate a slower but larger memory type. A cache has some maximum size that is much smaller than the larger storage area.

15. L1 cache L1 cache L2 cache L2 cache Physical memory Physical memory Virtual memory storage Virtual memory storage CPU When using a cache, you must check the cache to see if an item is in there. If it is there, it's called a cache hit. Otherwise, it is called a cache miss and the computer must wait for a round trip from the larger and slower memory area.

16. Associative Memory  Cache memory can be constructed using either SRAM or associative memory.  SRAM is accessed just like most other types of memory: It receives an address and accesses the data at that address.  Associative memory is accessed differently.

17.  it searches all of its locations in parallel and marks the locations that match the specified data input. How to access data in associative memory?  The matching data are then read out sequentially

18. To accessed data in the associative memory that has 1010 as its four high order bits. Example 1010 xxxx xxxx xxxx The 4 learding bits are the value to be matched, so the remaining 12 bits can have any value.

19. The CPU first loads the value 1010 xxxx xxxx xxxx into the data register. Data register Mask register Memory Output register Match register Read Data Write 0000 1111 0000 1011 1000 0000 1000 1000 0011 1101 1111 1111 0100 1001 1000 1000 0011 1101 0011 0000 1010 0000 1010 1101 0000 0111 1010 0000 0000 0000 10110101011010 V

20. Each bit that is to be checked, regardless of the value it should have, is set to 1; all the other bits are set to zero. 1010 xxxx xxxx xxxx 1111 0000 0000 0000

21. CPU then load the value 1111 0000 0000 0000 into the mask register. Data register Mask register Memory Output register Match register Read Data Write 0000 1111 0000 1011 1000 0000 1000 1000 0011 1101 1111 1111 0100 1001 1000 1000 0011 1101 0011 0000 1010 0000 1010 1101 0000 0111 1010 0000 0000 0000 1011011010110110 V

22. Data register Mask register Memory Output register Match register Read Data Write 0000 1111 0000 1011 1000 0000 1000 1000 0011 1101 1111 1111 0100 1001 1000 1000 0011 1101 0011 0000 1010 0000 1010 1101 0000 0111 1010 0000 0000 0000 1011011010110110 V At this point, the associative memory checks each location in parallel.

23. The four leading bits are to be matched in the match register and the rest can be anything. Data 0000 1111 0000 1011 1000 0000 1000 1000 0011 1101 1111 1111 0100 1001 1000 1000 0011 1101 0011 0000 1010 0000 1010 1101 0000 0111 1010 0000 0000 0000 1011011010110110 V 1010

24.  Note that each word has one additional bit labeled v (valid bit).  1 is for valid data.  0 is for not valid data. Data register Mask register Memory Output register Match register Read Data Write 0000 1111 0000 1011 1000 0000 1000 1000 0011 1101 1111 1111 0100 1001 1000 1000 0011 1101 0011 0000 1010 0000 1010 1101 0000 0111 1010 0000 0000 0000 1011011010110110 V

25. A match occurs if for every bit position that has a value of 1 in the mask register and the location of that valid bit is set to 1. Otherwise it’s set to zero. Data 0000 1111 0000 1011 1000 0000 1000 1000 0011 1101 1111 1111 0100 1001 1000 1000 0011 1101 0011 0000 1010 0000 1010 1101 0000 0111 1010 0000 0000 0000 1011011010110110 V 1010

26. Cache Organization Direct mapped map each memory address into a specified cache location. Full associative any memory location can be stored in any line of cache Set associative cache divided into k-sets of cache lines line in memory may be placed anywhere within a set

27. As you can see in the memory system, the L1 cache caches the L2 cache, which caches the physical memory, which can be used to cache the disk subsystems, and so on. L1 cache L1 cache L2 cache L2 cache Physical memory Physical memory Virtual memory storage Virtual memory storage CPU