1. 1 ECE 545 – Introduction to VHDL ECE 545 Lecture 4 Behavioral & Structural Design Styles

2. 2 ECE 545 – Introduction to VHDL Resources Volnei A. Pedroni, Circuit Design with VHDL Chapter 6, Sequential Code (sections 6.1-6.4) Chapter 10, Packages and Components Chapter 7.1, Constant Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 4, Registers and Latches Chapter 9, Design Partitioning

3. 3 ECE 545 – Introduction to VHDL Behavioral Design Style for Testbenches

4. 4 ECE 545 – Introduction to VHDL VHDL Design Styles Components and interconnects structural VHDL Design Styles dataflow Concurrent statements behavioral Testbenches Sequential statements

5. 5 ECE 545 – Introduction to VHDL Anatomy of a Process [label:] process [(sensitivity list)] [declaration part] begin statement part end process [label]; OPTIONAL

6. 6 ECE 545 – Introduction to VHDL Statement Part Contains Sequential Statements to be Executed Each Time the Process Is Activated Analogous to Conventional Programming Languages

7. 7 ECE 545 – Introduction to VHDL A process can be given a unique name using an optional LABEL This is followed by the keyword PROCESS The keyword BEGIN is used to indicate the start of the process All statements within the process are executed SEQUENTIALLY. Hence, order of statements is important. A process must end with the keywords END PROCESS. TESTING: process begin TEST_VECTOR<=“00”; wait for 10 ns; TEST_VECTOR<=“01”; wait for 10 ns; TEST_VECTOR<=“10”; wait for 10 ns; TEST_VECTOR<=“11”; wait for 10 ns; end process; A process is a sequence of instructions referred to as sequential statements. What is a PROCESS? The Keyword PROCESS

8. 8 ECE 545 – Introduction to VHDL Execution of statements in a PROCESS The execution of statements continues sequentially till the last statement in the process. After execution of the last statement, the control is again passed to the beginning of the process. Testing: PROCESS BEGIN test_vector<=“00”; WAIT FOR 10 ns; test_vector<=“01”; WAIT FOR 10 ns; test_vector<=“10”; WAIT FOR 10 ns; test_vector<=“11”; WAIT FOR 10 ns; END PROCESS; Order of execution Program control is passed to the first statement after BEGIN

9. 9 ECE 545 – Introduction to VHDL PROCESS with a WAIT Statement The last statement in the PROCESS is a WAIT instead of WAIT FOR 10 ns. This will cause the PROCESS to suspend indefinitely when the WAIT statement is executed. This form of WAIT can be used in a process included in a testbench when all possible combinations of inputs have been tested or a non-periodical signal has to be generated. Testing: PROCESS BEGIN test_vector<=“00”; WAIT FOR 10 ns; test_vector<=“01”; WAIT FOR 10 ns; test_vector<=“10”; WAIT FOR 10 ns; test_vector<=“11”; WAIT; END PROCESS; Program execution stops here Order of execution

10. 10 ECE 545 – Introduction to VHDL WAIT FOR vs. WAIT WAIT FOR: waveform will keep repeating itself forever WAIT : waveform will keep its state after the last wait instruction. 0 123 … 0 123 …

11. 11 ECE 545 – Introduction to VHDL PROCESS with a SENSITIVITY LIST List of signals to which the process is sensitive. Whenever there is an event on any of the signals in the sensitivity list, the process fires. Every time the process fires, it will run in its entirety. WAIT statements are NOT ALLOWED in a processes with SENSITIVITY LIST. label: process (sensitivity list) declaration part begin statement part end process;

12. 12 ECE 545 – Introduction to VHDL Testbenches

13. 13 ECE 545 – Introduction to VHDL Generating selected values of one input SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0); BEGIN....... testing: PROCESS BEGIN test_vector <= "000"; WAIT FOR 10 ns; test_vector <= "001"; WAIT FOR 10 ns; test_vector <= "010"; WAIT FOR 10 ns; test_vector <= "011"; WAIT FOR 10 ns; test_vector <= "100"; WAIT FOR 10 ns; END PROCESS;........ END behavioral;

14. 14 ECE 545 – Introduction to VHDL Generating all values of one input SIGNAL test_vector : STD_LOGIC_VECTOR(3 downto 0):="0000"; BEGIN....... testing: PROCESS BEGIN WAIT FOR 10 ns; test_vector <= test_vector + 1; end process TESTING;........ END behavioral;

15. 15 ECE 545 – Introduction to VHDL SIGNAL test_ab : STD_LOGIC_VECTOR(1 downto 0); SIGNAL test_sel : STD_LOGIC_VECTOR(1 downto 0); BEGIN....... double_loop: PROCESS BEGIN test_ab <="00"; test_sel <="00"; for I in 0 to 3 loop for J in 0 to 3 loop wait for 10 ns; test_ab <= test_ab + 1; end loop; test_sel <= test_sel + 1; end loop; END PROCESS;........ END behavioral; Generating all possible values of two inputs

16. 16 ECE 545 – Introduction to VHDL Generating periodical signals, such as clocks CONSTANT clk1_period : TIME := 20 ns; CONSTANT clk2_period : TIME := 200 ns; SIGNAL clk1 : STD_LOGIC; SIGNAL clk2 : STD_LOGIC := ‘0’; BEGIN....... clk1_generator: PROCESS clk1 <= ‘0’; WAIT FOR clk1_period/2; clk1 <= ‘1’; WAIT FOR clk1_period/2; END PROCESS; clk2 <= not clk2 after clk2_period/2;....... END behavioral;

17. 17 ECE 545 – Introduction to VHDL Generating one-time signals, such as resets CONSTANT reset1_width : TIME := 100 ns; CONSTANT reset2_width : TIME := 150 ns; SIGNAL reset1 : STD_LOGIC; SIGNAL reset2 : STD_LOGIC := ‘1’; BEGIN....... reset1_generator: PROCESS reset1 <= ‘1’; WAIT FOR reset_width; reset1 <= ‘0’; WAIT; END PROCESS; reset2_generator: PROCESS WAIT FOR reset_width; reset2 <= ‘0’; WAIT; END PROCESS;....... END behavioral;

18. 18 ECE 545 – Introduction to VHDL Typical error SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0); SIGNAL reset : STD_LOGIC; BEGIN....... generator1: PROCESS reset <= ‘1’; WAIT FOR 100 ns reset <= ‘0’; test_vector <="000"; WAIT; END PROCESS; generator2: PROCESS WAIT FOR 200 ns test_vector <="001"; WAIT FOR 600 ns test_vector <="011"; END PROCESS;....... END behavioral;

19. 19 ECE 545 – Introduction to VHDL Behavioral Design Style for Synthesis

20. 20 ECE 545 – Introduction to VHDL Register Transfer Level (RTL) Design Description Combinational Logic Combinational Logic Registers …

21. 21 ECE 545 – Introduction to VHDL VHDL Design Styles Components and interconnects structural VHDL Design Styles dataflow Concurrent statements behavioral Registers & counters Sequential statements

22. 22 ECE 545 – Introduction to VHDL Component Equivalent of a Process All signals which appear on the left of signal assignment statement (<=) are outputs e.g. y, z All signals which appear on the right of signal assignment statement (<=) or in logic expressions are inputs e.g. w, a, b, c All signals which appear in the sensitivity list are inputs e.g. clk Note that not all inputs need to be included in the sensitivity list priority: PROCESS (clk) BEGIN IF w(3) = '1' THEN y <= "11" ; ELSIF w(2) = '1' THEN y <= "10" ; ELSIF w(1) = c THEN y <= a and b; ELSE z <= "00" ; END IF ; END PROCESS ; w a y z priority b c clk

23. 23 ECE 545 – Introduction to VHDL Processes in VHDL Processes Describe Sequential Behavior Processes in VHDL Are Very Powerful Statements Allow to define an arbitrary behavior that may be difficult to represent by a real circuit Not every process can be synthesized Use Processes with Caution in the Code to Be Synthesized Use Processes Freely in Testbenches

24. 24 ECE 545 – Introduction to VHDL Registers

25. 25 ECE 545 – Introduction to VHDL ClockD 0 1 1 – 0 1 0 1 Truth table Graphical symbol t 1 t 2 t 3 t 4 Time Clock D Q Timing diagram Q(t+1) Q(t) D latch D Q Clock

26. 26 ECE 545 – Introduction to VHDL Clk D   0 1 0 1 Truth table t 1 t 2 t 3 t 4 Time Clock D Q Timing diagram Q(t+1) Q(t) D flip-flop D Q Clock Graphical symbol 0 – Q(t) 1 –

27. 27 ECE 545 – Introduction to VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY latch IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END latch ; ARCHITECTURE Behavior OF latch IS BEGIN PROCESS ( D, Clock ) BEGIN IF Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior; D latch D Q Clock

28. 28 ECE 545 – Introduction to VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock: INSTD_LOGIC ; Q: OUTSTD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior_1 OF flipflop IS BEGIN PROCESS ( Clock ) BEGIN IF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior_1 ; D flip-flop (1) D Q Clock

29. 29 ECE 545 – Introduction to VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock: INSTD_LOGIC ; Q: OUTSTD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior_1 OF flipflop IS BEGIN PROCESS ( Clock ) BEGIN IF rising_edge(Clock) THEN Q <= D ; END IF ; END PROCESS ; END Behavior_1 ; D flip-flop (2) D Q Clock

30. 30 ECE 545 – Introduction to VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock: INSTD_LOGIC ; Q: OUTSTD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior_2 OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; Q <= D ; END PROCESS ; END Behavior_2 ; D flip-flop (3) D Q Clock

31. 31 ECE 545 – Introduction to VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock: INSTD_LOGIC ; Q: OUTSTD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior_2 OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL rising_edge(Clock) ; Q <= D ; END PROCESS ; END Behavior_2 ; D flip-flop (4) D Q Clock

32. 32 ECE 545 – Introduction to VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= '0' ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; D flip-flop with asynchronous reset D Q Clock Resetn

33. 33 ECE 545 – Introduction to VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF Resetn = '0' THEN Q <= '0' ; ELSE Q <= D ; END IF ; END PROCESS ; END Behavior ; D flip-flop with synchronous reset D Q Clock Resetn

34. 34 ECE 545 – Introduction to VHDL 8-bit register with asynchronous reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY reg8 IS PORT ( D: IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; Resetn, Clock: IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; END reg8 ; ARCHITECTURE Behavior OF reg8 IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= "00000000" ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ;` Resetn Clock reg8 88 DQ

35. 35 ECE 545 – Introduction to VHDL N-bit register with asynchronous reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regn IS GENERIC ( N : INTEGER := 16 ) ; PORT ( D: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Resetn, Clock: IN STD_LOGIC ; Q: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ; ARCHITECTURE Behavior OF regn IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q '0') ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; Resetn Clock regn NN DQ

36. 36 ECE 545 – Introduction to VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regn IS GENERIC ( N : INTEGER := 8 ) ; PORT (D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable, Clock: IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ; ARCHITECTURE Behavior OF regn IS BEGIN PROCESS (Clock) BEGIN IF (Clock'EVENT AND Clock = '1' ) THEN IF Enable = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; N-bit register with enable Q D Enable Clock regn NN

37. 37 ECE 545 – Introduction to VHDL Counters

38. 38 ECE 545 – Introduction to VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY upcount IS PORT (Clear, Clock: IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0) ) ; END upcount ; ARCHITECTURE Behavior OF upcount IS BEGIN upcount: PROCESS ( Clock ) BEGIN IF (Clock'EVENT AND Clock = '1') THEN IF Clear = '1' THEN Q <= "00" ; ELSE Q <= Q + “01” ; END IF ; END PROCESS; END Behavior ; 2-bit up-counter with synchronous reset Q Clear Clock upcount 2

39. 39 ECE 545 – Introduction to VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY upcount IS PORT ( Clock, Resetn, Enable : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ; END upcount ; 4-bit up-counter with asynchronous reset (1) Q Enable Clock upcount 4 Resetn

40. 40 ECE 545 – Introduction to VHDL ARCHITECTURE Behavior OF upcount IS SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ; BEGIN PROCESS ( Clock, Resetn ) BEGIN IF Resetn = '0' THEN Count <= "0000" ; ELSIF (Clock'EVENT AND Clock = '1') THEN IF Enable = '1' THEN Count <= Count + 1 ; END IF ; END PROCESS ; Q <= Count ; END Behavior ; 4-bit up-counter with asynchronous reset (2) Q Enable Clock upcount 4 Resetn

41. 41 ECE 545 – Introduction to VHDL Shift Registers

42. 42 ECE 545 – Introduction to VHDL Shift register DQ Sin Clock DQDQDQ Q(3) Q(2) Q(1)Q(0) Enable

43. 43 ECE 545 – Introduction to VHDL Shift Register With Parallel Load D(3) DQ Clock Enable Sin D(2) DQ D(1) DQ D(0) DQ Q(0)Q(1)Q(2)Q(3) Load

44. 44 ECE 545 – Introduction to VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY shift4 IS PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; Enable: IN STD_LOGIC ; Load: IN STD_LOGIC ; Sin : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END shift4 ; 4-bit shift register with parallel load (1) Q Enable Clock shift4 4 D Load Sin 4

45. 45 ECE 545 – Introduction to VHDL ARCHITECTURE Behavior_1 OF shift4 IS BEGIN PROCESS (Clock) BEGIN IF Clock'EVENT AND Clock = '1' THEN IF Load = '1' THEN Q <= D ; ELSIF Enable = ‘1’ THEN Q(0) <= Q(1) ; Q(1) <= Q(2); Q(2) <= Q(3) ; Q(3) <= Sin; END IF ; END PROCESS ; END Behavior_1 ; 4-bit shift register with parallel load (2) Q Enable Clock shift4 4 D Load Sin 4

46. 46 ECE 545 – Introduction to VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY shiftn IS GENERIC ( N : INTEGER := 8 ) ; PORT (D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable: IN STD_LOGIC ; Load: IN STD_LOGIC ; Sin : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END shiftn ; N-bit shift register with parallel load (1) Q Enable Clock shiftn N D Load Sin N

47. 47 ECE 545 – Introduction to VHDL ARCHITECTURE Behavior OF shiftn IS BEGIN PROCESS (Clock) BEGIN IF (Clock'EVENT AND Clock = '1' ) THEN IF Load = '1' THEN Q <= D ; ELSIF Enable = ‘1’ THEN Genbits: FOR i IN 0 TO N-2 LOOP Q(i) <= Q(i+1) ; END LOOP ; Q(N-1) <= Sin ; END IF; END PROCESS ; END Behavior ; N-bit shift register with parallel load (2) Q Enable Clock shiftn N D Load Sin N

48. 48 ECE 545 – Introduction to VHDL If Statement

49. 49 ECE 545 – Introduction to VHDL Sequential Statements (1) If Statement else and elsif are optional if boolean expression then statements elsif boolean expression then statements else boolean expression then statements end if;

50. 50 ECE 545 – Introduction to VHDL SELECTOR: process begin WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF Sel = “00” THEN f <= x1; ELSIF Sel = “10” THEN f <= x2; ELSE f <= x3; END IF; end process; If Statement - Example

51. 51 ECE 545 – Introduction to VHDL Structural Design Style

52. 52 ECE 545 – Introduction to VHDL VHDL Design Styles Components and interconnects structural VHDL Design Styles dataflow Concurrent statements behavioral Registers & counters Sequential statements

53. 53 ECE 545 – Introduction to VHDL Structural VHDL component instantiation (port map) generate scheme for component instantiations (for-generate) component instantiation with generic (generic map, port map) Major instructions

54. 54 ECE 545 – Introduction to VHDL Structural VHDL component instantiation (port map) component instantiation with generic (generic map, port map) generate scheme for component instantiations (for-generate) Major instructions

55. 55 ECE 545 – Introduction to VHDL Circuit built of medium scale components w 0 w 3 y 0 y 1 z w 1 w 2 w 0 En y 0 w 1 y 1 y 2 y 3 s(0) 0 1 s(1) 0 1 r(0) r(1) r(2) r(3) r(4) r(5) p(0) p(1) p(2) p(3) q(0) q(1) ena z(0) z(1) z(2) z(3) dec2to4 priority z(0) z(1) z(2) z(3) regn DQ Clk Clock Enable En

56. 56 ECE 545 – Introduction to VHDL 2-to-1 Multiplexer (a) Graphical symbol (b) Truth table 0 1 f s w 0 w 1 f s w 0 w 1 0 1

57. 57 ECE 545 – Introduction to VHDL VHDL code for a 2-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT (w0, w1, s : INSTD_LOGIC ; f : OUTSTD_LOGIC ) ; END mux2to1 ; ARCHITECTURE dataflow OF mux2to1 IS BEGIN f <= w0 WHEN s = '0' ELSE w1 ; END dataflow ;

58. 58 ECE 545 – Introduction to VHDL Priority Encoder d 0 0 1 0 1 0 w 0 y 1 d y 0 11 0 1 1 1 1 z 1 x x 0 x w 1 0 1 x 0 x w 2 0 0 1 0 x w 3 0 0 0 0 1 w 0 w 3 y 0 y 1 z w 1 w 2

59. 59 ECE 545 – Introduction to VHDL VHDL code for a Priority Encoder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY priority IS PORT (w: IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; y: OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; z: OUT STD_LOGIC ) ; END priority ; ARCHITECTURE dataflow OF priority IS BEGIN y <="11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE "01" WHEN w(1) = '1' ELSE "00" ; z <= '0' WHEN w = "0000" ELSE '1' ; END dataflow ;

60. 60 ECE 545 – Introduction to VHDL 2-to-4 Decoder 0 0 1 1 1 0 1 y 0 w 1 0 w 0 xx 1 1 0 1 1 En 0 0 0 1 0 y 1 1 0 0 0 0 y 2 0 1 0 0 0 y 3 0 0 1 0 0 w 0 y 0 w 1 y 1 y 2 y 3 (a) Truth table(b) Graphical symbol

61. 61 ECE 545 – Introduction to VHDL VHDL code for a 2-to-4 Decoder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT (w: IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END dec2to4 ; ARCHITECTURE dataflow OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= “0001" WHEN "100", "0010" WHEN "101", "0100" WHEN "110", “1000" WHEN "111", "0000" WHEN OTHERS ; END dataflow ;

62. 62 ECE 545 – Introduction to VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regn IS GENERIC ( N : INTEGER := 8 ) ; PORT (D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable, Clock: IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ; ARCHITECTURE Behavior OF regn IS BEGIN PROCESS (Clock) BEGIN IF (Clock'EVENT AND Clock = '1' ) THEN IF Enable = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; N-bit register with enable Q D Enable Clock regn NN

63. 63 ECE 545 – Introduction to VHDL Circuit built of medium scale components w 0 w 3 y 0 y 1 z w 1 w 2 w 0 En y 0 w 1 y 1 y 2 y 3 s(0) 0 1 s(1) 0 1 r(0) r(1) r(2) r(3) r(4) r(5) p(0) p(1) p(2) p(3) q(0) q(1) ena z(0) z(1) z(2) z(3) dec2to4 priority t(0) t(1) t(2) t(3) regn DQ Clk Clock Enable En

64. 64 ECE 545 – Introduction to VHDL Structural description – example (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY priority_resolver IS PORT (r: IN STD_LOGIC_VECTOR(5 DOWNTO 0) ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; clk : IN STD_LOGIC; en : IN STD_LOGIC; t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END priority_resolver; ARCHITECTURE structural OF priority_resolver IS SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ; SIGNAL z : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL ena : STD_LOGIC ;

65. 65 ECE 545 – Introduction to VHDL Structural description – example (2) COMPONENT mux2to1 PORT (w0, w1, s : INSTD_LOGIC ; f : OUTSTD_LOGIC ) ; END COMPONENT ; COMPONENT priority PORT (w: IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; y: OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; z: OUT STD_LOGIC ) ; END COMPONENT ; COMPONENT dec2to4 PORT (w: IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END COMPONENT ;

66. 66 ECE 545 – Introduction to VHDL Structural description – example (3) COMPONENT regn GENERIC ( N : INTEGER := 8 ) ; PORT (D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable, Clock: IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END COMPONENT ;

67. 67 ECE 545 – Introduction to VHDL Structural description – example (4) BEGIN u1: mux2to1 PORT MAP (w0 => r(0), w1 => r(1), s => s(0), f => p(0)); p(1) <= r(2); p(1) <= r(3); u2: mux2to1 PORT MAP (w0 => r(4), w1 => r(5), s => s(1), f => p(3)); u3: priority PORT MAP (w => p, y => q, z => ena); u4: dec2to4 PORT MAP (w => q, En => ena, y => z);

68. 68 ECE 545 – Introduction to VHDL Structural description – example (5) u5: regn GENERIC MAP (N => 4) PORT MAP (D => z, Enable => En, Clock => Clk, Q => t ); END structural;

69. 69 ECE 545 – Introduction to VHDL Named association connectivity recommended in majority of cases, prevents ommisions and mistakes COMPONENT dec2to4 PORT (w: IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END COMPONENT ; u4: dec2to4 PORT MAP (w => q, En => ena, y => z);

70. 70 ECE 545 – Introduction to VHDL COMPONENT dec2to4 PORT (w: IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END COMPONENT ; u4: dec2to4 PORT MAP (w, En, y); Positional association connectivity allowed, especially for the cases of small number of ports multiple instantiations of the same component, in regular structures

71. 71 ECE 545 – Introduction to VHDL Structural description with positional association connectivity BEGIN u1: mux2to1 PORT MAP (r(0), r(1), s(0), p(0)); p(1) <= r(2); p(1) <= r(3); u2: mux2to1 PORT MAP (r(4), r(5), s(1), p(3)); u3: priority PORT MAP (p, q, ena); u4: dec2to4 PORT MAP (q, ena, z); u5: regn GENERIC MAP(4) PORT MAP (z, En, Clk, t); END structural;

72. 72 ECE 545 – Introduction to VHDL Packages

73. 73 ECE 545 – Introduction to VHDL Package – example (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; PACKAGE GatesPkg IS COMPONENT mux2to1 PORT (w0, w1, s : INSTD_LOGIC ; f : OUTSTD_LOGIC ) ; END COMPONENT ; COMPONENT priority PORT (w: IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; y: OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; z: OUT STD_LOGIC ) ; END COMPONENT ;

74. 74 ECE 545 – Introduction to VHDL Package – example (2) COMPONENT dec2to4 PORT (w: IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END COMPONENT ; COMPONENT regn GENERIC ( N : INTEGER := 8 ) ; PORT (D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable, Clock: IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END COMPONENT ;

75. 75 ECE 545 – Introduction to VHDL constant ADDAB : std_logic_vector(3 downto 0) := "0000"; constant ADDAM : std_logic_vector(3 downto 0) := "0001"; constant SUBAB : std_logic_vector(3 downto 0) := "0010"; constant SUBAM : std_logic_vector(3 downto 0) := "0011"; constant NOTA : std_logic_vector(3 downto 0) := "0100"; constant NOTB : std_logic_vector(3 downto 0) := "0101"; constant NOTM : std_logic_vector(3 downto 0) := "0110"; constant ANDAB : std_logic_vector(3 downto 0) := "0111"; END GatesPkg; Package – example (3)

76. 76 ECE 545 – Introduction to VHDL Package usage (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE work.GatesPkg.all; ENTITY priority_resolver IS PORT (r: IN STD_LOGIC_VECTOR(5 DOWNTO 0) ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; clk : IN STD_LOGIC; en : IN STD_LOGIC; t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END priority_resolver; ARCHITECTURE structural OF priority_resolver IS SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ; SIGNAL z : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL ena : STD_LOGIC ;

77. 77 ECE 545 – Introduction to VHDL BEGIN u1: mux2to1 PORT MAP (w0 => r(0), w1 => r(1), s => s(0), f => p(0)); p(1) <= r(2); p(1) <= r(3); u2: mux2to1 PORT MAP (w0 => r(4), w1 => r(5), s => s(1), f => p(3)); u3: priority PORT MAP (w => p, y => q, z => ena); u4: dec2to4 PORT MAP (w => q, En => ena, y => z); Package usage (2)

78. 78 ECE 545 – Introduction to VHDL u5: regn GENERIC MAP (N => 4) PORT MAP (D => z, Enable => En, Clock => Clk, Q => t ); END structural; Package usage (3)

79. 79 ECE 545 – Introduction to VHDL Constants

80. 80 ECE 545 – Introduction to VHDL Constants Syntax: CONSTANT name : type := value; Examples: CONSTANT init_value : STD_LOGIC_VECTOR(3 downto 0) := "0100"; CONSTANT ANDA_EXT : STD_LOGIC_VECTOR(7 downto 0) := X"B4"; CONSTANT counter_width : INTEGER := 16; CONSTANT buffer_address : INTEGER := 16#FFFE#; CONSTANT clk_period : TIME := 20 ns; CONSTANT strobe_period : TIME := 333.333 ms;

81. 81 ECE 545 – Introduction to VHDL Constants - features Constants can be declared in a PACKAGE, ENTITY, ARCHITECTURE When declared in a PACKAGE, the constant is truly global, for the package can be used in several entities. When declared in an ARCHITECTURE, the constant is local, i.e., it is visible only within this architecture. When declared in an ENTITY declaration, the constant can be used in all architectures associated with this entity.

82. 82 ECE 545 – Introduction to VHDL Component Configuration

83. 83 ECE 545 – Introduction to VHDL Configuration declaration CONFIGURATION SimpleCfg OF priority_resolver IS FOR structural FOR ALL: mux2to1 USE ENTITY work.mux2to1(dataflow); END FOR; FOR u3: priority USE ENTITY work.priority(dataflow); END FOR; FOR u4: dec2to4 USE ENTITY work.dec2to4(dataflow); END FOR; END SimpleCfg;

84. 84 ECE 545 – Introduction to VHDL Configuration specification LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE work.GatesPkg.all; ENTITY priority_resolver IS PORT (r: IN STD_LOGIC_VECTOR(5 DOWNTO 0) ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; z : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END priority_resolver; ARCHITECTURE structural OF priority_resolver IS SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ; SIGNAL ena : STD_LOGIC ; FOR ALL: mux2to1 USE ENTITY work.mux2to1(dataflow); FOR u3: priority USE ENTITY work.priority(dataflow); FOR u4: dec2to4 USE ENTITY work.dec2to4(dataflow);

85. 85 ECE 545 – Introduction to VHDL Mixing Design Styles Inside of an Architecture

86. 86 ECE 545 – Introduction to VHDL architecture ARCHITECTURE_NAME of ENTITY_NAME is Here you can declare signals, constants, functions, procedures… Component declarations No variable declarations !! begin Concurrent statements: Concurrent simple signal assignment Conditional signal assignment Selected signal assignment Generate statement Component instantiation statement Process statement inside process you can use only sequential statements end ARCHITECTURE_NAME; Mixed Style Modeling Concurrent Statements

87. 87 ECE 545 – Introduction to VHDL Generate scheme for components

88. 88 ECE 545 – Introduction to VHDL Structural VHDL component instantiation (port map) component instantiation with generic (generic map, port map) generate scheme for component instantiations (for-generate) Major instructions

89. 89 ECE 545 – Introduction to VHDL Example 1

90. 90 ECE 545 – Introduction to VHDL w 8 w 11 s 1 w 0 s 0 w 3 w 4 w 7 w 12 w 15 s 3 s 2 f Example 1

91. 91 ECE 545 – Introduction to VHDL A 4-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4to1 IS PORT (w0, w1, w2, w3: IN STD_LOGIC ; s: IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f: OUT STD_LOGIC ) ; END mux4to1 ; ARCHITECTURE Dataflow OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END Dataflow ;

92. 92 ECE 545 – Introduction to VHDL Straightforward code for Example 1 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Example1 IS PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ; s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END Example1 ;

93. 93 ECE 545 – Introduction to VHDL Straightforward code for Example 1 ARCHITECTURE Structure OF Example1 IS COMPONENT mux4to1 PORT (w0, w1, w2, w3: IN STD_LOGIC ; s: INSTD_LOGIC_VECTOR(1 DOWNTO 0) ; f: OUT STD_LOGIC ) ; END COMPONENT ; SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ; Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ; Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ; Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ; Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ;

94. 94 ECE 545 – Introduction to VHDL Modified code for Example 1 ARCHITECTURE Structure OF Example1 IS COMPONENT mux4to1 PORT (w0, w1, w2, w3: IN STD_LOGIC ; s: INSTD_LOGIC_VECTOR(1 DOWNTO 0) ; f: OUT STD_LOGIC ) ; END COMPONENT ; SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN G1: FOR i IN 0 TO 3 GENERATE Muxes: mux4to1 PORT MAP ( w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ; END GENERATE ; Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ;

95. 95 ECE 545 – Introduction to VHDL Example 2

96. 96 ECE 545 – Introduction to VHDL Example 2 w 0 En y 0 w 1 y 1 y 2 y 3 y 8 y 9 y 10 y 11 w 2 w 0 y 0 y 1 y 2 y 3 w 0 En y 0 w 1 y 1 y 2 y 3 w 0 y 0 w 1 y 1 y 2 y 3 y 4 y 5 y 6 y 7 w 1 w 0 y 0 w 1 y 1 y 2 y 3 y 12 y 13 y 14 y 15 w 0 En y 0 w 1 y 1 y 2 y 3 w 3 w

97. 97 ECE 545 – Introduction to VHDL A 2-to-4 binary decoder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w: IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END dec2to4 ; ARCHITECTURE Dataflow OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "1000" WHEN "100", "0100" WHEN "101", "0010" WHEN "110", "0001" WHEN "111", "0000" WHEN OTHERS ; END Dataflow ;

98. 98 ECE 545 – Introduction to VHDL VHDL code for Example 2 (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec4to16 IS PORT (w: IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; En : IN STD_LOGIC ; y: OUT STD_LOGIC_VECTOR(0 TO 15) ) ; END dec4to16 ;

99. 99 ECE 545 – Introduction to VHDL VHDL code for Example 2 (2) ARCHITECTURE Structure OF dec4to16 IS COMPONENT dec2to4 PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y: OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END COMPONENT ; SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN G1: FOR i IN 0 TO 3 GENERATE Dec_ri: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(i), y(4*i TO 4*i+3) ); G2: IF i=3 GENERATE Dec_left: dec2to4 PORT MAP ( w(i DOWNTO i-1), En, m ) ; END GENERATE ; END Structure ;

100. 100 ECE 545 – Introduction to VHDL Example 3 Variable Rotator

101. 101 ECE 545 – Introduction to VHDL Example 3: Variable rotator - Interface 16 4 A B C A <<< B

102. 102 ECE 545 – Introduction to VHDL Block diagram

103. 103 ECE 545 – Introduction to VHDL VHDL code for a 16-bit 2-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1_16 IS PORT (w0: IN STD_LOGIC_VECTOR(15 DOWNTO 0); w1: IN STD_LOGIC_VECTOR(15 DOWNTO 0); s : INSTD_LOGIC ; f : OUTSTD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END mux2to1_16 ; ARCHITECTURE dataflow OF mux2to1_16 IS BEGIN f <= w0 WHEN s = '0' ELSE w1 ; END dataflow ;

104. 104 ECE 545 – Introduction to VHDL Fixed rotation a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13) <<< 3 a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13) a(12) a(11) <<< 5

105. 105 ECE 545 – Introduction to VHDL VHDL code for for a fixed 16-bit rotator LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fixed_rotator_left_16 IS GENERIC ( L : INTEGER := 1); PORT (a: IN STD_LOGIC_VECTOR(15 DOWNTO 0); y: OUTSTD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END fixed_rotator_left_16 ; ARCHITECTURE dataflow OF fixed_rotator_left_16 IS BEGIN y <= a(15-L downto 0) & a(15 downto 15-L+1); END dataflow ;

106. 106 ECE 545 – Introduction to VHDL Structural VHDL code for for a variable 16-bit rotator (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY variable_rotator_16 is PORT( A : IN STD_LOGIC_VECTOR(15 downto 0); B : IN STD_LOGIC_VECTOR(3 downto 0); C : OUT STD_LOGIC_VECTOR(15 downto 0) ); END variable_rotator_16;

107. 107 ECE 545 – Introduction to VHDL Structural VHDL code for for a variable 16-bit rotator (2) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ARCHITECTURE structural OF variable_rotator_16 IS COMPONENT mux2to1_16 PORT (w0: IN STD_LOGIC_VECTOR(15 DOWNTO 0); w1: IN STD_LOGIC_VECTOR(15 DOWNTO 0); s : INSTD_LOGIC ; f : OUTSTD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END COMPONENT ; COMPONENT fixed_rotator_left_16 GENERIC ( L : INTEGER := 1); PORT (a: IN STD_LOGIC_VECTOR(15 DOWNTO 0); y: OUTSTD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END COMPONENT ;

108. 108 ECE 545 – Introduction to VHDL Structural VHDL code for for a variable 16-bit rotator (3) TYPE array1 IS ARRAY (0 to 4) OF STD_LOGIC_VECTOR(15 DOWNTO 0); TYPE array2 IS ARRAY (0 to 3) OF STD_LOGIC_VECTORS(15 DOWNTO 0); SIGNAL Al : array1; SIGNAL Ar : array2; BEGIN Al(0) <= A; G: FOR i IN 0 TO 3 GENERATE ROT_I: fixed_rotator_left_16 GENERIC MAP (L => 2** i) PORT MAP ( a => Al(i), y => Ar(i)); MUX_I: mux2to1_16 PORT MAP (w0 => Al(i), w1 => Ar(i), s => B(i), f => Al(i+1)); END GENERATE; C <= Al(4); END variable_rotator_16;

109. 109 ECE 545 – Introduction to VHDL Example 4 N-bit Comparator

110. 110 ECE 545 – Introduction to VHDL Example 4: Iterative circuits: 8-bit comparator A(7)B(7) CMP_IN(1) CMP_IN(0) A(6)B(6)A(0)B(0) CMP_OUT(1) CMP_OUT(0) entity COMPARE8 is port( A, B: in STD_LOGIC_VECTOR(7 downto 0); CMP_IN: in STD_LOGIC_VECTOR(1 downto 0); CMP_OUT: out STD_LOGIC_VECTOR(1 downto 0)); end COMPARE8; COMPARE8

111. 111 ECE 545 – Introduction to VHDL 8-bit comparator: Truth Table CMP_INCMP_OUT 00 00 if A=B 1 if A>B 01 if A<B 10 10 independently of A and B 01 01 independently of A and B 11 (invalid inputs) --

112. 112 ECE 545 – Introduction to VHDL AB X_OUT Y_OUT BIT_COMPARE entity BIT_COMPARE is port(A, B, X_IN, Y_IN: in STD_LOGIC; X_OUT, Y_OUT: out STD_LOGIC); end BIT_COMPARE; X_IN Y_IN Basic building block

113. 113 ECE 545 – Introduction to VHDL X_IN & Y_INX_OUT & Y_OUT 00 00 if A=B 1 if A=‘1’ and B=‘0’ 01 if A=‘0’ and B=‘1’ 10 10 independently of A and B 01 01 independently of A and B 11 (invalid inputs) -- Basic building block – Truth Table

114. 114 ECE 545 – Introduction to VHDL 8-bit comparator - Architecture A(7)B(7) CMP_IN(1) CMP_IN(0) A(6)B(6)A(0)B(0) CMP_OUT(1) CMP_OUT(0) INT_X(7) INT_X(1) INT_Y(7) INT_Y(1) INT_X(6) INT_Y(6)

115. 115 ECE 545 – Introduction to VHDL architecture STRUCTURE of COMPARE8 is component BIT_COMPARE port(A, B, X_IN, Y_IN: in STD_LOGIC; X_OUT, Y_OUT: out STD_LOGIC); end component; signal INT_X, INT_Y: STD_LOGIC_VECTOR(7 downto 1); begin C7: BIT_COMPARE port map(A(7), B(7), CMP_IN(1), CMP_IN(0), INT_X(7), INT_Y(7)); C6: BIT_COMPARE port map(A(6), B(6), INT_X(7), INT_Y(7), INT_X(6), INT_Y(6));... C0: BIT_COMPARE port map(A(0), B(0), INT_X(1), INT_Y(1), CMP_OUT(0), CMP_OUT(1)); end STRUCTURE; Architecture without for-generate

116. 116 ECE 545 – Introduction to VHDL 8-bit comparator - Architecture A(7)B(7) CMP_IN(1) CMP_IN(0) A(6)B(6)A(0)B(0) CMP_OUT(1) CMP_OUT(0) INT_X(7)INT_X(1) INT_Y(7) INT_Y(1) INT_X(8) INT_Y(8) INT_X(0) INT_Y(0)

117. 117 ECE 545 – Introduction to VHDL architecture STRUCTURE of COMPARE8 is component BIT_COMPARE port(A, B, X_IN, Y_IN: in STD_LOGIC; X_OUT, Y_OUT: out STD_LOGIC); end component; signal INT_X, INT_Y: STD_LOGIC_VECTOR(8 downto 0); begin INT_X(8) <= CMP_IN(1); INT_Y(8) <= CMP_IN(0); CASCADE: for I in 7 downto 0 generate C: BIT_COMPARE port map(A(I), B(I), INT_X(I+1), INT_Y(I+1), INT_X(I), INT_Y(I)); end generate; CMP_OUT(1) <= INT_X(0); CMP_OUT(0) <= INT_Y(0); end STRUCTURE; Architecture with for-generate

118. 118 ECE 545 – Introduction to VHDL N-bit Comparator – Entity declaration entity COMPAREN is generic(N: positive); -- N – width of operands port( A, B: in BIT_VECTOR(N-1 downto 0); CMP_IN: in BIT_VECTOR(1 downto 0); CMP_OUT: out BIT_VECTOR(1 downto 0)); end COMPAREN;

119. 119 ECE 545 – Introduction to VHDL architecture STRUCTURE of COMPAREN is component BIT_COMPARE port(A, B, X_IN, Y_IN: in STD_LOGIC; X_OUT, Y_OUT: out STD_LOGIC); end component; signal INT_X, INT_Y: STD_LOGIC_VECTOR(N downto 0); begin INT_X(N) <= CMP_IN(1); INT_Y(N) <= CMP_IN(0); CASCADE: for I in N-1 downto 0 generate C: BIT_COMPARE port map(A(I), B(I), INT_X(I+1), INT_Y(I+1), INT_X(I), INT_Y(I)); end generate; CMP_OUT(1) <= INT_X(0); CMP_OUT(0) <= INT_Y(0); end STRUCTURE; N-bit Comparator – Architecture

120. 120 ECE 545 – Introduction to VHDL component COMPAREN generic(N: positive); -- N – width of operands port( A, B: in STD_LOGIC_VECTOR(N downto 0); CMP_IN: in STD_LOGIC_VECTOR(1 downto 0); CMP_OUT: out STD_LOGIC_VECTOR(1 downto 0)); end component; ……… CMP8: COMPAREN generic map(N => 16) port map(A => P1, B => P2, CMP_IN => SIG_IN, CMP_OUT => SIG_OUT ); N-bit Comparator – Instantiation