1. Front End Circuit.

2. CZT FRONT END ELECTRONICS INTERFACE CZTASIC FRONT END ELECTRONICS TO PROCESSING ELECTRONICS -500 V BIAS+/-2V +/-15V I/O signal

3. 1.It is fully data driven charge signal acquisition chip. 2. All Analog and Digital outputs are current driven for 1µs. Each pixel is addressable. 3. Provision of programming for needed parameters of the chip like threshold, shaping time constant and various other parameter. ClkIn and RegIn are Clock and Input for the Shift- registor. 4. The chip requires +2 and -2 volts for operation. 5. Daisy chaining of chips. FEATURES OF ASIC XaIm3.2

4. SignallevelsRemarks Dvdd+ 2 V Digital positive supply. Dvss- 2 V Digital negative supply. Avdd+2 V Analog positive supply. Avss- 2 V Analog negative supply. Gnd0 V Analog ground. Dgnd0 V Digital ground. Aoutp0 to 200µA Pulse height value of hit channel. Aoutm0 to -200µA Pulse height value of hit channel. Mgo60 µAMagnitude of Mgo determines the no. of hits. Io#15 – Io#00-100 µATo get output in digital form use transimpedence amplifier. Logic 1 = 100 µA, Logic 0 = 0µA MaRes p 100 mVResets the ASIC. Reg In+/- 2 VLogic 1 = +2 V, Logic 0 = -2 V Clk in+/- 2 VData at Reg In is sampled at falling edge of clock. Reg Out+/- 2 VLogic 1 = +2 V, Logic 0 = -2 V I/O Interface to Front End Electronics

5. ASIC control signals SignalDescriptionAdjustement VthrDiscriminator threshold voltage Int. DAC, ext. overriding possible. IfsBias current feedback resistance shaper IfpBias current feedback resistance preamp TrigWbiasBias-current for data-output duration Sha_biasBias-current for shaper Ls_biasRef. voltage for analog output buffer TrigDelBiasBias-current for delay of trigger MbiasBias-current for internal bias generation network Int. DAC. ResWbiasBias-current for internal reset durationExternal overriding possible. Ota_biasBias-current for peak-hold and discriminator MaResPReset of the chip+ 100mV *

6. Outline of Amplifier channel aout ctout in

7. Functional Block Diagram

8. Data acquisition in ASIC at each event  Hit pixel collected charge pulse is amplified & filtered in pre-amp & shaper.  Peak detector detects the peak of the pulse.  If peak value is larger than threshold, trigger signal will be generated.  Hit pixel trigger signal + Analogue peak value + Channel address. (Readout period = 1µs).  The chip resets itself after Readout period.

9. 321 DAISY CHAINING OF ASIC Upto 512 chips can be daisy chained on a common shared bus. Options for us:- 128 individual lines for each ASIC. 128 ASIC daisy chained. 32 ASIC daisy chained, so 4 quadrant.(32 x 4) REG IN REG OUT CLK IN

11. Sequence of Serial shift register mask back

12.  Power Rails : DVdd = +2V,DVss = -2V AVdd = +2V,AVss = -2V  Read out = Self triggered & data driven  Analog output = 0-200 µA  Read out time = 1 µS  Channels = 128  Peaking time = Nominal : 0.5 µS Adjustable : 0.35 µS – 1 µS  Power Dissipation = 3.2 mW / channel  Can be easily daisy chained. ASIC Specifications

13. M1M2M3Mn ADDR BUS DATA BUS TRIG & MULTI HIT DATA CLOCK ENERGY PULSE