1. This material exempt per Department of Commerce license exception TSU Multi-rate Systems

2. Objectives After completing this module, you will be able to: Define multi-channel and multi-rate systems Identify sample rate changing blocks Describe Simulink propagation rules Explain the hardware realization for rate changing blocks

3. Outline Multi-rate Systems Sample Rate Changing Blocks Simulink Propagation Rules Hardware Lab 6: Designing a MAC FIR

4. BPF LPF EqualizationDemodulation BPF LPF EqualizationDemodulation R.F. 40-150 MHz5-40 MHz500 kHz - 10 MHz Sample Rates Multi-rate Systems Looking at a typical wireless base-station receiver application, we can see that filters can form a major part of the DSP functionality Because the object of such a system is to down convert from high frequencies to lower frequencies, however, this is also coupled with many different sample rates …

5. BPF LPF EqualizationDemodulation BPF LPF EqualizationDemodulation R.F. 40-150 MHz5-40 MHz500 kHz - 10 MHz Sample Rates Multi-rate Systems How are sample rate changes performed in System Generator? What tools are available to build multi-rate systems and what are the difficulties and problems involved?

6. Sample Times…Again? Every SysGen signal must be sampled; that is, transitions occur at equidistant discrete points in time called sample times – Set explicitly Gateway in Blocks w/o inputs (note: constants are idiosyncratic) – Derived from input sample times – System sample period controlled by System Generator token – What if the sample rate needs to be changed?

7. Outline Multi-rate Systems Sample Rate Changing Blocks Simulink Propagation Rules Hardware Lab 6: Designing a MAC FIR

8. Sample Rate Changing Blocks Up sample can either replicate the same number M-1 times or insert M-1 zeros to achieve the higher sampling rate Down sample “throws away” M-1 samples to achieve lower sampling rate Up Sample by 3 00 Down Sample by 3 0 0

9. Sample Rate Changing Blocks Parallel to Serial: Output rate will be M times faster, where M is the width of the input parallel data Serial to Parallel: Output rate will be M times slower, where M is the width of the output parallel data FIR: Can be used as a polyphase interpolation or decimation FIR

10. Too Many Rates! As designs grow, there are tools available to track and manage all the different sampling rates – Use Sample Time block from Xilinx Blockset  Index or Tools libraries – Use the sample time colors (Format  Sample Time Colors) – Use Simulink display block to view the output of the sample block

11. Sample Period (GCD) Sample Period Gateway InBlock OutputDown SampleUp SampleUp Sample1 0.11.30.260.13 10/100 130/10026/10013/100 Simulink System Period: 1/100 Who Runs the Show? The System Generator token still controls simulations. The “Simulink System Period” must be set correctly for simulation to work. The System Period is the global sample period that all other sample periods can be derived from. Therefore, every sample period in a design must be a multiple of the System period

12. Who Runs the Show? “Simulink System Period” MUST be set correctly for simulation to work If incorrect, the tools will calculate the value for you

13. 44.1 kHz 48 kHz 441 kHz CD format DAT format 7056 kHz Sample Period (GCD) Sample Period Gateway InBlockantiAliasFIRantiAliasFIR1Gateway Out Simulink System Sample Period: Exercise: Audio Application Analyze the following sampling rate change system that is commonly found in audio broadcasting studios. Determine the Simulink System Sample period:

14. Outline Multi-rate Systems Sample Rate Changing Blocks Simulink Propagation Rules Hardware Lab 6: Designing a MAC FIR

15. Simulink Propagation Rules Simulink’s data type and sample time inheritance rules make it possible to tailor design without having to update every block Simulink resolves all data types and sample times during initialization by propagating known values – As mentioned, all blocks inherit their input sample rate – Feedback loops no longer cause problems for Simulink’s propagation algorithms No longer required to set explicit sample time in every feedback loop – SysGen idiom: “explicit inherited” sample period tells Simulink to inherit first encountered sample time

16. Outline Multi-rate Systems Sample Rate Changing Blocks Simulink Propagation Rules Hardware Lab 6: Designing a MAC FIR

17. What About the Hardware? System Generator implements multi-rate systems using a synchronous clock enable scheme Every block gets the same system clock signal, the fastest clock, but is enabled at its relative sample rate defined in Simulink

18. What About the Hardware? How this works: – In hardware, think of the sample period as the “number clock pulses between block execution” E.g., a sample period of 1 means that particular block will be executed on every clk cycle. Hence, the system clock is assumed to have a sample period of “1.” A sample period of 5 means that particular block will be executed on every fifth clock cycle – SysGen examines every sample time in the entire system, and computes their greatest common divisor (GCD). The system clock corresponds to the GCD (sample period of ‘1’), and each sample period is then normalized to a multiple of this value – SysGen generates circuitry (xlclockdriver.vhd) that periodically asserts a CE (for a single clock cycle) for every required multiple. The main circuitry in the xlclockdriver.vhd is a counter and some comparator logic

19. What About the Hardware? This concept is illustrated below in a timing diagram. These Clock enable pulses are referred to as the “Normalized Sample Times”

20. What About the Hardware? This clocking scheme means the implementation tools need to be informed how fast each flip-flop really has to be clocked (i.e., multi- cycle path constraints are a must). Fortunately, in SysGen, the code generator does this (see XCF file)

21. Some Hardware Specifics To continue with our theme of ‘looking under the hood’ it is important to examine the hardware implementation and potential traps associated with using multi-rate systems We will examine the: – Up Sampler – Down Sampler

22. L Up Sampler Up sampler becomes a “short” (a wire) if samples are copied. There is no cost in hardware, simply a simulation construct Otherwise, a MUX switches between 0 and the data input

23. Up Sampler L

24. Latency > 0 has two options – Sample Last Value of Frame is most efficient (a delay) – Sample First Value (costs one additional register) Down Sampler

25. Latency > 0 has two options – Sample Last Value of Frame is most efficient (a delay) – Sample First Value (costs one additional register) M Down Sampler

26. Latency zero has a shutter, but has a registered enable Careful of the combinatorial feedthrough path on the data line through the output MUX. This is a problem with zero-latency down samplers

27. Useful Blocks Use the CLK probe and the CE Probe from the Xilinx Blockset to view their respective signals CE Probe produces Boolean output that can be used for control logic

28. Hint: Refer to the up/down sampler slides to help determine their respective sample times Exercise: Audio Application Analyze the following sampling rate change system that is commonly found in audio broadcasting studios. Fill in the sampling rates in the table below: DAT format DAB format 32 kHz 96 kHz 48 kHz

29. Outline Multi-rate Systems Sample Rate Changing Blocks Simulink Propagation Rules Hardware Lab 6: Designing a MAC FIR

30. In this lab, you will create a MAC-based FIR filter in System Generator using the MAC engine that you created in Lab 1 and control logic that you created in Lab 5. The purpose of this lab is to solidify the concepts covered thus far, by implementing a larger, more complex DSP function than the functions addressed earlier.