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مرتضي صاحب الزماني 1 Synthesis. مرتضي صاحب الزماني 2 Synthesis What is Synthesis? RTL-style Combinatorial Logic Sequential Logic Finite State Machines.

Published byDarrell Martin Modified over 8 years ago

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Presentation on theme: "مرتضي صاحب الزماني 1 Synthesis. مرتضي صاحب الزماني 2 Synthesis What is Synthesis? RTL-style Combinatorial Logic Sequential Logic Finite State Machines."— Presentation transcript:

1 مرتضي صاحب الزماني 1 Synthesis

2 مرتضي صاحب الزماني 2 Synthesis What is Synthesis? RTL-style Combinatorial Logic Sequential Logic Finite State Machines and VHDL

3 مرتضي صاحب الزماني 3 What is Synthesis? Transformation of an abstract description into a more detailed description "+" operator is transformed into a gate netlist "if (VEC_A = VEC_B) then"  a comparator which controls a multiplexer Transformation depends on several factors: Algorithm, constraints, library عملگرهاي ساده ( مثل AND ، OR ، مقايسه ) به گيتهاي مشخصي تبديل مي شوند اما عملگرهاي پيچيده تر مثل ضرب ابتدا به ماکروسلهاي خاص آن tool تبديل مي شوند.

4 مرتضي صاحب الزماني 4 Synthesizability Only a subset of VHDL is synthesizable Different Tools support different subsets records? arrays of integers? clock edge detection? sensitivity list?...

5 مرتضي صاحب الزماني 5 Different Language Support for Synthesis

6 مرتضي صاحب الزماني 6 How to Do? Macrocells adder comparator bus interface counter Constraints speed area power Optimizations boolean: mathematic LUTs: technological LUTs

7 مرتضي صاحب الزماني 7 Constraints محدوديتهاي سخت : محدوديتهاي ثابتي که در سنتزکننده وجود دارد : مربوط به محدوديتهاي target technology ( مثل محدوديت fanout در Logic Block ها ) و مربوط به توانايي tool محدوديتهاي نرم : محدوديتهايي که کاربر مشخص مي کند : مثل حداقل سرعت لازم

8 مرتضي صاحب الزماني 8 Non-functional requirements Performance: –Clock speed is generally a primary requirement. –Usually expressed as a lower bound. Design cycle and Timing Closure Size: –Determines manufacturing cost. –If your design doesn’t fit into one size FPGA, you must use the next larger FPGA. –For very large designs: multi-FPGAs. Power/energy: –Power/Energy related to battery life and heat. May have more cost: –More expensive packaging to dissipate heat. –More extreme measures (e.g. cooling fans). –Many digital systems are power- or energy-limited.

9 مرتضي صاحب الزماني 9 Mapping into an FPGA Must choose the FPGA: –Capacity. –Pinout/package type. –Maximum speed.

10 مرتضي صاحب الزماني 10 Capacity

11 مرتضي صاحب الزماني 11 Pinout Description

12 مرتضي صاحب الزماني 12 Essential Information for Synthesis Load values Path delays Driver strengths Timing Operating conditions (e.g. temperature)

13 مرتضي صاحب الزماني 13 Synthesis Process in Practice باوجود مکانيزمهاي بهينه سازي، ممکن است بعد از سنتز، همة محدوديتها برآورده نشده باشند  تکرار SynthesisDesign EntryResults OK? yes no Alter Constraints Alter VHDL Code Arch’re Design Alter Arch’re

14 مرتضي صاحب الزماني 14 Problems with Synthesis Tools Timing issues layout information is missing during the synthesis process clock tree must be generated afterwards Complex clocking schemes (inverted clocks, multiple clocks, gated clocks) Memory synthesis tools are not able to replace register arrays with memory macro cells Macro cells no standardized way for instantiation of existing technology macro cells

15 مرتضي صاحب الزماني 15 Synthesis Strategy Consider the effects of different coding styles on the inferred hardware structures Appropriate design partitioning critical paths should not be distributed to several synthesis blocks different optimization constraints may be used for separate blocks

16 مرتضي صاحب الزماني 16 Delay and Power Optimization Combinational network delay. Combinational network energy/power.

17 مرتضي صاحب الزماني 17 Delay characteristics Measured from change in inputs to change in outputs. Data-dependent: –Some block delays depend on the value/waveform at the input (t pHL ≠ t pLH ) (t r ≠ t f ) May need to observe different paths through the network.

18 مرتضي صاحب الزماني 18 Timing diagram time A B

19 مرتضي صاحب الزماني 19 Sources of Delay Gate delay: –Little we can do about it E.g. select another FPGA with faster logic blocks (LBs) or Minimize the number of LBs in the critical path Wire delay: –Much we can do E.g. select the proper path of the wire or Select buffered paths. –Two types: lumped load (for short wires which are modeled by a single capacitance) –Little we can do. transmission line (for long wires).

20 مرتضي صاحب الزماني 20 Fanout Fanout adds capacitance. source sink

21 مرتضي صاحب الزماني 21 Driving fanout Adding gates adds capacitance:

22 مرتضي صاحب الزماني 22 Path delay Combinational network delay is measured over paths through network. Can trace a causality chain from inputs to worst-case output.

23 مرتضي صاحب الزماني 23 Path delay example network graph model

24 مرتضي صاحب الزماني 24 Critical path Critical path = path which creates longest delay. Can trace transitions which cause delays that are elements of the critical delay path.

25 مرتضي صاحب الزماني 25 Delay model Nodes represent gates. Assign delays to edges—signal may have different delay to different sinks. Lump gate and wire delay into a single value.

26 مرتضي صاحب الزماني 26 Critical path through delay graph

27 مرتضي صاحب الزماني 27 Reducing critical path length Must speed up the critical path –Reducing delay off the path doesn’t help. There may be more than one path of the same delay. –  Must speed up all equivalent paths to speed up circuit. Cutset: a set of edges that when removed, break the graph into two unconnected paths. (e.g. {(C,D), (B,D)} or {(D,E} ) –Must speed up cutset through critical path.

28 مرتضي صاحب الزماني 28 Delay Paths in a design

29 مرتضي صاحب الزماني 29 False paths Some input changes don’t cause output changes. A false path is a path which never happens due to Boolean gate conditions. False paths cause pessimistic delay estimates.

30 مرتضي صاحب الزماني 30 False path example (input dependent)

31 مرتضي صاحب الزماني 31 Another false path example (input independent)  = 10  = 20  = 10  = 20 False path

32 مرتضي صاحب الزماني 32 Placement and delay Placement helps determine gate distances. Gate distances determine routing. Routing determines wire length. Wire length determines capacitive load. Capacitive load determines delay.

33 مرتضي صاحب الزماني 33 Placement and wire capacitance dvr g1 g2 g3 g4 dvr g1 g2 g3 g4

34 مرتضي صاحب الزماني 34 Optimizing network delay Identify the longest path(s). Improve delay along the longest path(s): –Driver delay –Wire delay –Logic restructuring NET "data_out_1_OBUF" ROUTE="{3;1;6slx25csg324;477afbc1!-1;8040;6064;S!0;-845;-504!1;0;344!1;" "-9743;1431!2;845;144;L!3;-16261;1!5;-22484;-4!6;-17991;3!7;-12477;5681!8;" "0;12800!9;0;12800!10;0;12800!11;0;13872!12;0;12800!13;0;12800!14;0;12800!" "15;0;13872!16;305;7589!17;0;3200!18;1855;1675!19;686;18!20;80;20!21;" "- 1490;2207!22;-1311;251;L!}"; NET "data_out_1" LOC=D6; INST "data_out_1_OBUF" LOC=SLICE_X29Y41; INST "data_out_1" LOC=SLICE_X29Y41;

35 مرتضي صاحب الزماني 35 Example: Adder placement and delay N-bit adder: (optimal placement) ++++

36 مرتضي صاحب الزماني 36 Bad placement and routing placement routing With no delay constraints.

37 مرتضي صاحب الزماني 37 Bad placement and routing Adder has been distributed throughout the FPGA. I/O pins have been spread around the chip.  P&R algorithms do not catch on to regularity.

38 مرتضي صاحب الزماني 38 Better placement and routing With delay constraints. Better but far from optimal (less spread out horizontally but spread out vertically)

39 مرتضي صاحب الزماني 39 How to improve? Use macros (optimized), Put constraints on the placement of objects, Hand place objects. –Example: later.

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