2. Development of high speed waveform sampling ASICs Stefan Ritt - Paul Scherrer Institute, Switzerland NSNI – 2010, Mumbai, India

3. Feb. 25th, 2010NSNI-2010 Mumbai2 Question … 4 channels 5 GSPS 1 GHz BW 8 bit (6-7) 15k$ (700kRs) 4 channels 5 GSPS 1 GHz BW 8 bit (6-7) 15k$ (700kRs) 4 channels 5 GSPS 1 GHz BW 11.5 bits 1k$ (50kRs) USB Power 4 channels 5 GSPS 1 GHz BW 11.5 bits 1k$ (50kRs) USB Power

4. Feb. 25th, 2010NSNI-2010 Mumbai3 Switched Capacitor Array Shift Register Clock IN Out “Time stretcher” GHz  MHz Waveform stored Inverter “Domino” ring chain 0.2-2 ns FADC 33 MHz

5. Feb. 25th, 2010NSNI-2010 Mumbai4 Switched Capacitor Array Cons No continuous acquisition Limited sampling depth Nonlinear timing Pros High speed (up to 5 GSPS) high resolution (13 bit SNR) High channel density (16 channels on 5x5 mm 2 ) Low power (10-40 mW / channel) Low cost (~ 10$ / channel) tt tt tt tt tt Goal: Minimize Limitations

6. Feb. 25th, 2010NSNI-2010 Mumbai5 CMOS process (typically 0.35 … 0.13  m)  sampling speed Number of channels, sampling depth, differential input PLL for frequency stabilization Input buffer or passive input Analog output or (Wilkinson) ADC Internal trigger Design Options PLL ADC Trigger

7. Write Circuitry How to sample the input signal

8. Feb. 25th, 2010NSNI-2010 Mumbai7 Simple inverter chain 100000 000000 10 000000 1 0 1000 1111 11111 11111 111111 11

9. Feb. 25th, 2010NSNI-2010 Mumbai8 Design of Inverter Chain PMOS > NMOS PMOS < NMOS

10. Feb. 25th, 2010NSNI-2010 Mumbai9 “Tail Biting” enable 1234 1 2 3 4 speed

11. Feb. 25th, 2010NSNI-2010 Mumbai10 Phase Locked Loop On-chip PLL can lock sampling frequency to external reference clock T Q Phase Comparator External Reference Clock Inverter Chain loop filter down 11 22 sampling speed control PLL up

12. Feb. 25th, 2010NSNI-2010 Mumbai11 Timing jitter t1t1 t2t2 t3t3 t4t4 t5t5 Inverter chain has transistor variations   t i between samples differ  “Fixed pattern aperture jitter” “Differential temporal nonlinearity” TD i =  t i –  t nominal “Integral temporal nonlinearity” TI i =  t i – i  t nominal “Random aperture jitter” = variation of  t i between measurements Inverter chain has transistor variations   t i between samples differ  “Fixed pattern aperture jitter” “Differential temporal nonlinearity” TD i =  t i –  t nominal “Integral temporal nonlinearity” TI i =  t i – i  t nominal “Random aperture jitter” = variation of  t i between measurements TD 1 TI 5

13. Feb. 25th, 2010NSNI-2010 Mumbai12 Fixed jitter calibration Fixed jitter is constant over time, can be measured and corrected for Several methods are commonly used Most use sine wave with random phase and correct for TD i on a statistical basis Fixed jitter is constant over time, can be measured and corrected for Several methods are commonly used Most use sine wave with random phase and correct for TD i on a statistical basis

14. Feb. 25th, 2010NSNI-2010 Mumbai13 Fixed Pattern Jitter Results TD i typically ~50 ps RMS @ 5 GHz TI i goes up to ~600 ps Jitter is mostly constant over time,  measured and corrected Residual random jitter 3-4 ps RMS

15. Feb. 25th, 2010NSNI-2010 Mumbai14 Achievable Timing Resolution After proper timing calibration, a “split pulse timing accuracy” of typically ~10 ps can be chieved D. Breton Picosecond Workshop Clermont-Ferrand, Jan 2010 D. Breton Picosecond Workshop Clermont-Ferrand, Jan 2010

16. Feb. 25th, 2010NSNI-2010 Mumbai15 What determines the BW? The analog bandwidth is given by the parasitic capacitance of the input bus and the input impedance Typically 20fF/cell+20pF (bus), 2-3  for bond wire  1 GHz BW An active input buffer does not really help 20 fF 20 pF Bond wire 2-3  “The best buffer is no buffer” – G. Varner

17. Feb. 25th, 2010NSNI-2010 Mumbai16 Cascaded Switched Capacitor Array Combines the advantage of a short input stage (32 cells) with a deep secondary sampling stage (32x32 cells) Estimated input BW: 5 GHz Sampling speed: 10 GSPS (130 nm) 100 ps sample time – 3.1 ns hold time Matches BW of fastest detectors (G-APD, MCP-PMT)  next generation of SCAs

18. Readout Circuitry How to read out sampled waveforms

19. Feb. 25th, 2010NSNI-2010 Mumbai18 Analog Readout Methods write read C... R (700  ) I U in write C U in “Differential Pair” IbIb V out I b /2 +-+- read write C (200fF) U in read I ~ kT

20. Feb. 25th, 2010NSNI-2010 Mumbai19 Digital Readout Wilkinson-type ADC requires only one comparator per sampling cell 12-bit counter + - + - latch DAC latch ramp voltage comparator ASIC FPGA

21. Feb. 25th, 2010NSNI-2010 Mumbai20 How to minimize dead time ? Fast analog readout: 30 ns / sample Parallel readout Region-of-interest readout Simultaneous write / read AD9222 12 bit 8 channels DRS4

22. Feb. 25th, 2010NSNI-2010 Mumbai21 DRS4 ROI readout mode readout shift register Trigger stop normal trigger stop after latency Delay delayed trigger stop Patent pending! 33 MHz e.g. 100 samples @ 33 MHz  3 us dead time  300,000 events / sec. e.g. 100 samples @ 33 MHz  3 us dead time  300,000 events / sec.

23. Feb. 25th, 2010NSNI-2010 Mumbai22 Simultaneous Write/Read Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 0 FPGA 0 0 0 0 0 0 0 1 Channel 0Channel 1 1 Channel 0 readout 8-fold analog multi-event buffer Channel 2 1 Channel 1 0 Expected crosstalk ~few mV

24. Feb. 25th, 2010NSNI-2010 Mumbai23 Current SCA ASICs Chip familySAM [1]LAB [2]DRS [3]Anusmriti [4] Max. sampling speed2.5 GSPS3.7 GSPS6 GSPS0.5 GSPS Analog Bandwidth300 MHz900 MHz950 MHz? Number of channels21-1691 SNR13.4 bits10 bits11.4 bits? Sampling depth144-2520256-64k1025-8192128 Readout time 650  s150  s – 10ms 30 ns * n samples 128  s Input BuffersYES NOYES Internal PLLYESNOYES ADCExternalInternalExternal Power/channel150-500 mW15-50 mW14-45 mW400 mW [1] E. Delagnes, D. Breton et al., NIM A567 (2006) 21 [2] G. Varner et al., NIM A583 (2007) 447 [3] S. Ritt, NIM A518 (2004) and http://drs.web.psi.chhttp://drs.web.psi.ch [4] M. Sukhwani et al., NSNI 2010

25. Advanced Topics Triggering, Channel Cascading, Waveform Analysis

26. Feb. 25th, 2010NSNI-2010 Mumbai25 How to measure best timing? Simulation of MCP with realistic noise and different discriminators J.-F. Genat et al., arXiv:0810.5590 (2008)

27. Feb. 25th, 2010NSNI-2010 Mumbai26 Flash ADC Technique 60 MHz 12 bit Q-sensitive Preamplifier PMT/APD Wire Shaper Shaper is used to optimize signals for “slow” 60 MHz FADC Shaping stage can only remove information from the signal Shaping is unnecessary if FADC is “fast” enough All operations (CFD, optimal filtering, integration) can be done digitally Shaper is used to optimize signals for “slow” 60 MHz FADC Shaping stage can only remove information from the signal Shaping is unnecessary if FADC is “fast” enough All operations (CFD, optimal filtering, integration) can be done digitally FADC TDC “Fast” 12 bit Transimpedance Preamplifier FADC PMT/APD Wire Digital Processing Amplitude Time Baseline Restoration

28. Feb. 25th, 2010NSNI-2010 Mumbai27 How fast is “fast” Nyquist-Shannon: Sampling rate must be 2x the highest frequency coming from detector Analog Bandwidth must match signal from detector Fastest pulses coming from Micro-Channel-Plate PMTs 3  m pores

29. Feb. 25th, 2010NSNI-2010 Mumbai28 Fastest pulses MCP-PMTs: 70 ps rise time  4-5 GHz BW  10 GSPS Cable should not limit bandwidth  Put digitizer onto detector Higher sampling speed only improves statistics J. Milnes, J. Howoth, Photek shift register input fast sampling stage secondary sampling stage................................. Aimed parameters: 5 GHz Bandwidth 10 GSPS Sampling Rate Aimed parameters: 5 GHz Bandwidth 10 GSPS Sampling Rate 10 GSPS 30 GSPS

30. Feb. 25th, 2010NSNI-2010 Mumbai29 Trigger and DAQ on same board All SCA applications need some kind of trigger  split signals Using a multiplexer in DRS4, input signals can simultaneously digitized at 65 MHz and sampled in the DRS FPGA can make local trigger (or global one) and stop DRS upon a trigger DRS readout (5 GSPS) though same 8-channel FADCs analog front end DRS FADC 12 bit 65 MHz MUX FPGA trigger LVDS SRAM DRS4 global trigger bus “Free” local trigger capability without additional hardware

31. Feb. 25th, 2010NSNI-2010 Mumbai30 Daisy-chaining of channels Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Domino Wave 1 clock 0 1 0 1 0 1 0 enable input enable input Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Domino Wave 1 clock 0 1 0 1 0 1 0 enable input enable input DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells Chip daisy-chaining possible to reach virtually unlimited sampling depth

32. Feb. 25th, 2010NSNI-2010 Mumbai31 Interleaved sampling delays (167ps/8 = 21ps) G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007) 6 GSPS * 8 = 48 GSPS Possible if delay is implemented on PCB

33. Feb. 25th, 2010NSNI-2010 Mumbai32 On-line waveform display click template fit pedestal histo  848 PMTs “virtual oscilloscope”

34. Feb. 25th, 2010NSNI-2010 Mumbai33 Pulse shape discrimination   Leading edge Decay time AC-coupling Reflections Example:  /  source in liquid xenon detector (or:  /p in air shower)

35. Feb. 25th, 2010NSNI-2010 Mumbai34  -distribution     = 21 ns   = 34 ns Waveforms can be clearly distinguished   = 21 ns   = 34 ns Waveforms can be clearly distinguished

36. Feb. 25th, 2010NSNI-2010 Mumbai35 Template Fit Determine “standard” PMT pulse by averaging over many events  “Template” Find hit in waveform Shift (“TDC”) and scale (“ADC”) template to hit Minimize  2 Compare fit with waveform Repeat if above threshold Store ADC & TDC values  Experiment 500 MHz sampling Pile-up can be detected if two hits are separated in time by ~rise time of signal

37. Feb. 25th, 2010NSNI-2010 Mumbai36 Do we still need crates? An empty crate slot costs ~1k$ (crate, interface/computer, cooling) Crate topologies requires long cables  Reduction of bandwidth Alternative: Put electronics on detectors MEG 3000 channels G. Varner Belle-TOF G. Varner Belle-TOF cPCI H. Friedrich WaveDREAM PSI/ETHZ H. Friedrich WaveDREAM PSI/ETHZ GBit Ethernet

38. Feb. 25th, 2010NSNI-2010 Mumbai37 Experiments using SCA ASCIs MAGIC-II MEG 3000 channels ANITA ANTARES H.E.S.S. Belle-TOF

39. Feb. 25th, 2010NSNI-2010 Mumbai38 Conclusions Fast waveform digitizing with SCA chips will have a big impact on experiments in the next future, replacing traditional ADCs and TDCs SCA community growing! Exchange of experience is important. Joining is easy (e.g. USB evaluation boards) New generation of SCA chips on the horizon

40. Feb. 25th, 2010NSNI-2010 Mumbai39 Thank You!