1. CSE477 L23 Memories.1Irwin&Vijay, PSU, 2002 CSE477 VLSI Digital Circuits Fall 2002 Lecture 23: Semiconductor Memories Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477www.cse.psu.edu/~mji www.cse.psu.edu/~cg477 [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

2. CSE477 L23 Memories.2Irwin&Vijay, PSU, 2002 Review: Basic Building Blocks  Datapath l Execution units -Adder, multiplier, divider, shifter, etc. l Register file and pipeline registers l Multiplexers, decoders  Control l Finite state machines (PLA, ROM, random logic)  Interconnect l Switches, arbiters, buses  Memory l Caches (SRAMs), TLBs, DRAMs, buffers

3. CSE477 L23 Memories.3Irwin&Vijay, PSU, 2002 Second Level Cache (SRAM) A Typical Memory Hierarchy Control Datapath Secondary Memory (Disk) On-Chip Components RegFile Main Memory (DRAM) Data Cache Instr Cache ITLB DTLB eDRAM Speed (ns):.1’s 1’s 10’s 100’s 1,000’s Size (bytes): 100’s K’s 10K’s M’s T’s Cost: highest lowest  By taking advantage of the principle of locality: l Present the user with as much memory as is available in the cheapest technology. l Provide access at the speed offered by the fastest technology.

4. CSE477 L23 Memories.4Irwin&Vijay, PSU, 2002 Semiconductor Memories RWMNVRWMROM Random Access Non-Random Access EPROMMask- programmed SRAM (cache, register file) FIFO/LIFOE 2 PROM DRAMShift Register CAM FLASHElectrically- programmed (PROM)

5. CSE477 L23 Memories.5Irwin&Vijay, PSU, 2002 Growth in DRAM Chip Capacity

6. CSE477 L23 Memories.6Irwin&Vijay, PSU, 2002 1D Memory Architecture Word 0 Word 1 Word 2 Word n-1 Word n-2 Storage Cell m bits n words S0S0 S1S1 S2S2 S3S3 S n-2 S n-1 Input/Output n words  n select signals Word 0 Word 1 Word 2 Word n-1 Word n-2 Storage Cell m bits S0S0 S1S1 S2S2 S3S3 S n-2 S n-1 Input/Output A0A0 A1A1 A k-1 Decoder Decoder reduces # of inputs k = log 2 n

7. CSE477 L23 Memories.7Irwin&Vijay, PSU, 2002 2D Memory Architecture A0A0 Row Decoder A1A1 A j-1 Sense Amplifiers bit line word line storage (RAM) cell Row Address Column Address AjAj A j+1 A k-1 Read/Write Circuits Column Decoder 2 k-j m2 j Input/Output (m bits) amplifies bit line swing selects appropriate word from memory row

8. CSE477 L23 Memories.8Irwin&Vijay, PSU, 2002 3D Memory Architecture Row Addr Column Addr Block Addr Input/Output (m bits) Advantages: 1. Shorter word and/or bit lines 2. Block addr activates only 1 block saving power

9. CSE477 L23 Memories.9Irwin&Vijay, PSU, 2002 Read Only Memories (ROMs)

10. CSE477 L23 Memories.10Irwin&Vijay, PSU, 2002 Precharged MOS NOR ROM V dd precharge WL(0) WL(1) WL(2) WL(3) GND BL(0)BL(1)BL(2)BL(3)

11. CSE477 L23 Memories.11Irwin&Vijay, PSU, 2002 Precharged MOS NOR ROM V dd precharge WL(0) WL(1) WL(2) WL(3) GND BL(0)BL(1)BL(2)BL(3) 0  1 0 1 1 0 1 1 0

12. CSE477 L23 Memories.12Irwin&Vijay, PSU, 2002 MOS NOR ROM Layout Metal1 on top of diffusion Basic cell 10 x 7 WL(0) GND (diffusion) Metal1 Polysilicon Only 1 layer (contact mask) is used to program memory array, so programming of the ROM can be delayed to one of the last process steps. WL(1) WL(2) WL(3) GND (diffusion) BL(0)BL(1)BL(2)BL(3)

13. CSE477 L23 Memories.13Irwin&Vijay, PSU, 2002 Transient Model for NOR ROM WL BL C bit precharge c word metal1 poly r word Word line parasitics Resistance/cell: 35  Wire capacitance/cell: 0.65 fF Gate capacitance/cell: 5.10 fF Bit line parasitics Resistance/cell: 0.15  Wire capacitance/cell: 0.83 fF Drain capacitance/cell: 2.60 fF

14. CSE477 L23 Memories.14Irwin&Vijay, PSU, 2002 Propagation Delay of NOR ROM  Word line delay l Delay of a distributed rc-line containing M cells t word = 0.38(r word x c word ) M 2 = 20 nsec for M = 512  Bit line delay l Assuming min size pull-down and 3*min size pull-up with reduced swing bit lines (5V to 2.5V) C bit = 1.7 pF and I avHL = 0.36 mA so t HL = t LH = 5.9 nsec

15. CSE477 L23 Memories.15Irwin&Vijay, PSU, 2002 Read-Write Memories (RAMs)  Static – SRAM l data is stored as long as supply is applied l large cells (6 fets/cell) – so fewer bits/chip l fast – so used where speed is important (e.g., caches) l differential outputs (output BL and !BL) l use sense amps for performance l compatible with CMOS technology  Dynamic – DRAM l periodic refresh required l small cells (1 to 3 fets/cell) – so more bits/chip l slower – so used for main memories l single ended output (output BL only) l need sense amps for correct operation l not typically compatible with CMOS technology

16. CSE477 L23 Memories.16Irwin&Vijay, PSU, 2002 Memory Timing Definitions Read Read Cycle Read Access Write Write Cycle Data Write Setup Data Valid Write Hold

17. CSE477 L23 Memories.17Irwin&Vijay, PSU, 2002 4x4 SRAM Memory A0A0 Row Decoder !BL WL[0] A1A1 A2A2 Column Decoder sense amplifiers write circuitry BL WL[1] WL[2] WL[3] bit line precharge 2 bit words clocking and control enable read precharge BL[i]BL[I+1]

18. CSE477 L23 Memories.18Irwin&Vijay, PSU, 2002 2D Memory Configuration Row Decoder Sense Amps

19. CSE477 L23 Memories.19Irwin&Vijay, PSU, 2002 Decreasing Word Line Delay  Drive the word line from both sides  Use a metal bypass  Use silicides polysilicon word line metal word line driver WL polysilicon word line metal bypass WL

20. CSE477 L23 Memories.20Irwin&Vijay, PSU, 2002 Decreasing Bit Line Delay (and Energy)  Reduce the bit line voltage swing l need sense amp for each column to sense/restore signal  Isolate memory cells from the bit lines after sensing (to prevent the cells from changing the bit line voltage further) - pulsed word line l generation of word line pulses very critical -too short - sense amp operation may fail -too long - power efficiency degraded (because bit line swing size depends on duration of the word line pulse) l use feedback signal from bit lines  Isolate sense amps from bit lines after sensing (to prevent bit lines from having large voltage swings) - bit line isolation

21. CSE477 L23 Memories.21Irwin&Vijay, PSU, 2002 Pulsed Word Line Feedback Signal  Dummy column l height set to 10% of a regular column and its cells are tied to a fixed value l capacitance is only 10% of a regular column ReadWord line Bit lines Complete Dummy bit lines 10% populated

22. CSE477 L23 Memories.22Irwin&Vijay, PSU, 2002 Pulsed Word Line Timing  Dummy bit lines have reached full swing and trigger pulse shut off when regular bit lines reach 10% swing Read Complete Word line Bit line Dummy bit line  V = V dd  V = 0.1V dd

23. CSE477 L23 Memories.23Irwin&Vijay, PSU, 2002 Bit Line Isolation sense Read sense amplifier bit lines isolate sense amplifier outputs  V = 0.1V dd  V = V dd

24. CSE477 L23 Memories.24Irwin&Vijay, PSU, 2002 6-transistor SRAM Cell !BLBL WL M1 M2 M3 M4 M5 M6Q !Q

25. CSE477 L23 Memories.25Irwin&Vijay, PSU, 2002 Next Lecture and Reminders  Next lecture l SRAM, DRAM, and CAM cores -Reading assignment – Rabaey, et al, 12.2.2-12.2.3  Reminders l Project final reports due December 5 th l Final grading negotiations/correction (except for the final exam) must be concluded by December 10 th l Final exam scheduled -Monday, December 16 th from 10:10 to noon in 118 and 121 Thomas